Tensilica's HiFi Audio DSP is the First IP Core to Support SRS's Advanced StudioSound HD Audio Suite for HDTVs

SRS StudioSound HD is the latest and most advanced all-in-one audio solution available for flat panel televisions and home theater sound bar manufacturers. Availability of SRS StudioSound HD on Tensilica's HiFi audio DSP further extends Tensilica's lead as the most popular audio IP core supplier for home entertainment systems. Thus implementation enables delivery of the most advanced audio enhancement solutions to DTV SOC makers worldwide.

Tensilica's Looking for an IT Engineer

We're looking for someone who can be esponsible for Cisco LAN and WAN environment as well as Wireless, Cisco VPN, firewall, VOIP and telecom. Click on the headline to find out more.

Updated White Paper on our Diamond Standard Family of 32-bit controller cores

Tensilica's Diamond Standard Series is a family of code-compatible, preconfigured 32-bit microprocessor and DSP Intellectual Property (IP) cores based on Tensilica's Xtensa Instruction Set Architecture (ISA). If you're looking for a standard controller, check these out. They range from very small, simple controllers to a very powerful VLIW-style core.

Two New Santa Clara, CA USA Jobs Posted

We have two new openings for experienced, senior engineers. We need a senior audio DSP engineer and a senior logic design engineer. Check out the full list of job openings on our web site.

IntegrIT’s Math Library Now Available for Tensilica’s HiFi Audio DSPs

The IntegrIT NatureDSP Math library simplifies the software development process for design teams that want to port their own software codecs to the HiFi Audio DSP. The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for implementation of typical digital signal processing functions which efficiently utilize the HiFi Audio DSP architecture. It contains highly optimized routines for filtering, FFT, matrix, trigonometric and other math operations.

"Tensilica's HiFi Audio DSP is very popular and in use in everything from cellular phones to digital radio and home entertainment products," stated Dmitry Paroshin, managing partner, IntegrIT. "Now, with this library, developers will get high-performance math functions that will speed their development efforts."

White Paper: Everything You Wanted to Know about Blu-ray Audio, but were afraid to hear

The Blu-ray disc format is mostly considered a visual medium. However, sound contributes substantially to the overall experience. Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.

Tensilica CTO Chris Rowen Presents at SDR'10 Thursday

Chris Rowen, Tensilica founder and chief technology officer, has been invited to present "Extensible Baseband DSPs, Tools and Multi-Core Architectures for Low-Power 4G SDR Silicon Platforms" at the upcoming SDR'10 event in Washington, D.C. SDR'10 focuses on reconfigurable radio technologies and Rowen's presentation will highlight Tensilica's second generation processor-based, multi-standard handset baseband reference architecture.

In addition, Rowen will participate in a panel discussion on "Comparing FPGA + C compilers with Multi-core Technology." This panel will look at the costs, programmability, performance, power, and time-to-market of multiprocessor designs versus FPGAs to see who will ultimately dominate future SDR platforms.

What/When:
"Extensible Baseband DSPs, Tools and Multi-Core Architectures for Low-Power 4G SDR Silicon Platforms"
Thursday, Dec. 2 at 3:25 p.m., Section 6A, Applications

"Comparing FPGA + C Compilers with Multi-core Technology"
Thursday, Dec. 2 at 5:10 p.m., Panel Session

Where:
SDR'10 will be held at the Hyatt Regency Crystal City in Washington, D.C. For more information, visit http://conference.wirelessinnovation.org

Happy Thanksgiving Everyone

Tensilica's US offices will be closed tomorrow and Friday. We'll be giving thanks for another good year and all the wonderful Thanksgiving food we'll be eating. We'll be back Monday, probably a pound or two heavier.

White Paper: How to Increase ASIC Performance with Long-Word Processors

By packing multiple operations into a wide 32- or 64-bit instruction word, FLIX technology allows designers to accelerate a broader class of “hot spots" in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.

White Paper on TIE - Tensilica Instructin Extensions

TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces. TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power. Read the white paper to find out more.

New Job Posting: Sr. Strategic Field Application Engineer

We are looking for someone who can work directly with customers in key technical pre-sales and post-sales roles to provide architectural and design consulting on the best use of Xtensa in a customer's ASIC design.

Have You Seen all the Smart Phones with Tensilica Inside?

The Samsung Capitvate and Ruby II, the Google Nexus One, the LG SH-400, the Sharp SH705ill, the Pantech Ease and Hush - see them by clicking on the headline.

White paper: Highest MHz Does Not Mean Highest Peformance

In fact, processors with high clock rates consume much more power because power dissipation rises faster than operating frequency. All major PC CPU vendors now offer multicore processors that run at lower clock frequencies than older generation single-core processors.

The same argument holds true for embedded processors, which is even more important for embedded products that operate under very tight power/energy budgets such as portable devices-because extending battery life is an important feature that improves product marketability-but it is also true for non-portable devices because consumers do not want noisy cooling fans in their set-top boxs or flt-panel televisions while IT managers want routers and switches that reduce electrical costs by minimizing energy consumption in the data centers. For these reasons, SOC development teams need to achieve performance goals while keeping a lid on clock rates.

Featured partner: Dolby Labs

Tensilica's HiFi 2 and HiFi EP Audio DSPs provide the widest range of support for the excellent software Dolby has to offer for home entertainment. See our complete list of codecs.

Happy Diwali

For our employees and friends in India, happy Diwali.

Cut DSP Development Time - Get High Performance from C - Read our White Paper

The magic is in the compiler technology. Learn how an advanced compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code.

Will Google TV be a Winner?

Yes, Tensilica's audio is designed into Google TV. But we're not the only ones who think Google TV will be a great platform. See this discussion.

White Paper: A PRocessor and DSP IP Selection Checklist

Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle.

Happy Almost Halloween

It's our annual trick-or-treat at Tensilica day. Aren't these girls cute?

Why Powerline Communications is Getting "Hot"

Pardon the pun, but we're seeing several customers designing Tensilica cores into powerline applications. This Gigaom article (click on headline) gives a nice overview.

Carbon Design Systems' New IP Exchange

Carbon Design Systems unveiled Carbon IP Exchange, a web portal with a rich library of system-level models from a variety of IP vendors, including Tensilica, to streamline the creation of virtual platforms for architecture analysis, performance optimization and pre-silicon software development. By making 100% accurate models of our bridge components available on Carbon IP Exchange, we are giving our customers the ability to make accurate decisions even earlier in the design cycle.

Try our SW Tools Free for 15 Days - You'll Like Them

We're so confident in the quality of our software tools that you can try them for free for 15 days. If you need a longer eval, just let us know. clikc on the headline to sign up.

Why Did DesignArt Networks Pick Tensilica for 4G SOC?

The new and disruptive DAN3000 4G SoC family employs multiple customized processor cores from Tensilica. The result is the first fully integrated 40nm multi-layer, multi-core SoC platform, delivering more than 1 Gbps in mobile broadband data throughput, ready for LTE Advanced applications. With the DAN3000 SoC family, DesignArt Networks integrated all radio access network (RAN) processing layers into one single-SoC architecture, eliminating cost, size and performance roadblocks to multi-gigabit 4G broadband services.

To find out why they picked Tensilica, click on the link on the headline.

White Paper: How to Avoid the Traps and Pitfalls of SOC Design

Chances are pretty good that your current SOC design approach is making your job much harder than it needs to be. Start out on an easier path with this white paper.

Get HD Radio Add-on for iPhone

If you're not going to buy a new car to get HD radio, you can get a simple iPhone add-on, sold exclusively at RadioShack, and carry HD radio and Tensilica with you everywhere you go.

Buy a 2011 Car and Support Tensilica

Our HiFi Audio is inside many 2011 cars. Audi. BMW. Ford. Hyundai. Jaguar. Kia. Land Rover, Lincoln. Mercedes. Mercury. Mini. Rolls-Royce. Scion. VW, Volvo. Which will you pick? I'm thinking Rolls. Guess I'll have to start saving up.

What Does It Mean to Use Processors in the SOC Dataplane?

If you're involved in SOC (system-on-chip) design, it's likely that you're putting lots of processors into every new design. While most embedded processor IP companies invest in making controllers for applications processing, Tensilica invests in processors for the SOC dataplane, where the hardest data-intensive work must be done. See our new company overview page for more details.

4M Wireless Completes LTE Protocol Stack Software for Tensilica's 3GPP LTE Reference Architecture

The 4M Wireless PS100 LTE protocol stack is a 3GPP Release 8 compliant implementation of the LTE protocol stack for User Equipment (UE) terminals. It consists of a fully optimized Layer 2, Layer 3, and NAS LTE protocol software enabling the highest uplink and downlink data rates. It is optimized for low power consumption and efficient processor utilization.

Tensilica's LTE total solution is really coming together! Maybe that's why it's so popular.

New White Paper: The What, Why, and How of Customizable Dataplane Processors (DPUs)

What is a DPU? What can DPUs do? Why would anyone want to use this type of processor? How can a DPU be used instead of creating hand-coded RTL hardware? These questions and more are answered in this white paper.

New white paper: 10 Reasons to Customize a Processor Core

There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. We'll give you 10 good reasons why you should consider customizing your core in your next SOC design.

Amazon Kindle - Tensilica Inside

Yes, Tensilica's inside the WiFi chip in the new WiFi-enabled, slimmer Amazon Kindle.

Over 150 Companies Design with Tensillica Cores

Who are Tensilica's customers? Click on the headline to find out. We have over 150 companies that have used Tensilica's cores in their chip designs. Some won't let us list their name, but the list still is very impressive.

D-Link's new Boxee Box based on Tensilica Audio

This innovative Intel-based box gives you Internet freedom on your TV. The Boxee Box lets you choose the TV shows you want to watch and the ones you want to pay for. No cable service necessary. It includes an incredible selection of movies in HD, as well as over 40,000 TV episodes from your favorite networks.

Fujitsu invest in Tensilica

“After working with Tensilica on the development of advanced performance on our mobile terminals we realized how important Tensilica’s DPU foundation has become to our engineers,” stated Minoru Sakata, President, Mobile Phones Unit, Fujitsu Limited. “Tensilica’s customizable DPUs help us get maximum performance with the lowest possible power in high throughput, signal processing-intensive mobile wireless devices.”

With Customizable Processors, You can Lower Power - Significantly

In fact, customized Xtensa DPUs can even rival the power efficiency of dedicated RTL blocks thanks to advanced, automated power minimization features auto-generated by the Xtensa Processor Generator that must be manually implemented in a custom RTL block design.

Use Customizable Processors as Basic SOC Building Blocks

Now there’s a real alternative to RTL design. You can use customizable Xtensa processors to finish your design much faster and add flexibility to adapt to changing standards or product requirements. Tensilica’s Xtensa processors provide both the I/O throughput and the computational performance previously only available with RTL design. The generated processor fully rivals the performance and efficiency of hand-coded RTL blocks with many concurrent operations, efficient data types and optimized multiple wide deep pipelines. Read this 5-page section for more information.

AppliedMicro Picks Tensilica for High-Throughput Comms Chip Design

"We selected Tensilica's DPUs because of their remarkable ability to be customized with high-bandwidth, efficient interfaces, such as FIFO-like queues, to quickly stream data into and out of the processor," stated Sean Campeau, AppliedMicro's senior manager of engineering. "These high-speed connections bypass the main system bus altogether, allowing us to implement functions in the processor that previously could only meet our performance targets by being implemented in RTL (register transfer level) logic. Implementing these functions in a processor speeds our design effort considerably and gives us a much more flexible solution."

Why Highest MHz Does Not Mean Highest Performance

Read this white paper to see how you can boost SOC performance without driving clock rates and power dissipation through the roof.

Why Not Use Processors in the SOC Dataplane?

Tensilica offers the core technology that overcomes the top four objections to using processors in the dataplane:
1. Data throughput - Tensilica allows designers to bypass the main system bus, just like a block of RTL.
2. Fit into hardware design flow - We provide glueless pin-level co-simulation of the ISS with Verilog simulators from the leading EDA companies.
3. Processing speed - Customization yields speeds 10 to 100 times that of traditional processors and DSPs.
4. Customization challenges - Our process is automated - you can't break our cores!

Need a ultra high performance 32-bit core? Look at the Diamond 570T

With a Dhrystone 2.1 rating of 1.59 DMPIS/MHz, the Diamond Standard 570T is powered by dual 32x32 SIMD MULs and a 32-bit integer divider. It has built-in 16-bit DSP instructions plus high-speed interfaces. Oh my, what a controller!

White paper: The 5 Pitfalls of 4G Baseband Design

As Tensilica has been working with its customers to design building blocks for LTE PHY designs, including the DSPs and forward-error-correction subsystems, we've realized five key pitfalls associated with LTE baseband development. Read this white paper to find out what we found out.

Blu-ray Audio White paper

Our white paper: "Everything you wanted to know about Blu-ray audio but were afraid to hear" is a must for anyone designing audio into these devices.

See Tensilica at SNUG Boston Sept. 21

We just signed up for the Mini Designer Community Expo at SNUG (the Synopsys Users Group) on Tuesday, Sept. 21 from 5-7 pm. Stop by if you're in the neighborhood. It's at the Boston Marriott Newton Hotel.

Free 15-day SW Tools Eval

Tensilica has a well-deserved reputation for having world-class hardware and software design tools. Now, you can experience these powerful tools for yourself. We're offering a free 15-day, single-user node-locked software evaluation license. This license includes the our complete software development toolchain, including: our world-class XCC Compiler; the Xtensa Xplorer graphical user environment that integrates code development, code analysis, simulation, and processor optimization tools into one familiar Eclipse-based GUI; and our class-leading simulation technology providing high-speed, instruction accurate, and pin-level accurate simulation models. In addition, users receive evaluation access to the online knowledge base on our technical support site.

Over 60 Audio Codecs for HiFi Audio DSP

Sure, we offer the most popular audio DSP core on the market. But what makes it so attractive is the huge list of software available that's already been optimized to really work well on this great architecture. Find out why Dolby, DTS and others have tested our software and it meets up to their exacting standards.

Tensilica in Wireless Device Design

From Bluetooth to Femtocells, Tensilica is designed in to a wide variety of wireless devices. Check out our customer gallery - wireless section (click on headline) and see what innovative devices we're in, including the Nintendo DS2, notebooks, wireless USB hubs, etc.

KPIT Cummins - Our Newest Authorized SOC Design Center

KPIT Cummins brings great expertise in ASIC designs for infotainment and consumer electronics applications. They have expertise in digital design combined with analog and mixes signal - perforce for designs for digital still cameras, Blu-ray DVD players, and mobile and handheld devices.

Over 150 Companies use Tensilica's Processors

I just updated the list of companies currently using Tensilica's DPUs. Over 150 companies are using or have used Tensilica's processors in their SOC designs. Click on the headline to read all about them.

Tensilica in Smart Phones

Tensilica is in the new generation of Smartphones, and we're just beginning to see them come out. Expect a lot more later this year. Visit our Customer Gallery for the latest designs.

10 Tips for Successful SOC Design

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.

Novatek Picks Tensilica's HiFi Audio DSP for Blu-ray Disc and DTV

“We selected Tensilica’s HiFi Audio DSP after extensive competitive benchmarking because it provides a low power and area efficient audio solution to meet the demanding requirements of the latest DTV and Blu-ray Disc standards with fully certified codecs,” stated J. H. Chang, Novatek’s senior vice president. “With over 60 pre-ported codecs available, Tensilica offered a combination of excellent technical solution coupled with the availability of a large array of software including post-processing solution.”

Yes, You Can Beat Moore's Law. Here's How.

Read our white paper. While it is feasible to build ASIC devices with more than 100 million transistors, designing these chips is a big challenge. Programmability vs efficiency trade-offs are examined, and suggestions are made for an improved ASIC design methodology using processors as basic building blocks.

The Xtensa Architecture White Paper

This white paper is our most popular because it discussed the essential foundation of all of Tensilica's processor cores.

Ap Note: Accelerating Radix-2 FFT

This document discusses a basic, but very powerful capability of TIE, the ability to define a register file of any arbitrary width and instructions that perform computations on the register file. Additional techniques, such as FUSION and SIMD, are introduced to show how to further improve performance, along with techniques to reduce gate count. These TIE techniques improve FFT performance by a factor of almost 100 times compared to a conventional processor. While the radix-2 FFT algorithm was chosen to illustrate the use of TIE on a relatively simple DSP algorithm, the techniques covered in this application note apply to accelerating any algorithm.

White Paper: A Designer's Guide to Video Pre- and Post Processing

HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after. Click on the headline above to read this white paper.

Use Tensilica's Cores for Control

While they excel as dataplane processors, Tensilica’s Diamond Standard and Xtensa processors are ideal control processors and can be used as-is or tailored to match your performance targets. Click on the headline above to find outmore.

SySDSoft Ports Complete LTE Protocol Stack to Tensilica's Atlas LTE Reference Architecture

SySDSoft's LTE Protocol Stack for UE combines highest-to-date data rates (290Mbps DL and 75Mbps UL simultaneous throughput) with a small footprint required in today's mobile platforms. SySDSoft has designed its LTE protocol stack leveraging its extensive experience in a myriad of wireless standards including WiMAX-2005 and CDMA-DO. The solution comprises Layer 2, Layer 3 and NAS following the 3GPP September Release. The Layer 2 solution comprises the MAC, RLC, and PDCP with optimized code for the time-critical ROHC, support for HW ciphering/deciphering, ARQ, and channel prioritization. The RRC (Layer 3) implementation supports the cell selection, mobility, paging, and connection establishment and release.

Tensilica's Atlas UE LTE reference architecture implements the complete 3GPP LTE Layer 1 PHY at CAT4 data rates based on its customizable and programmable Xtensa Dataplane Processors (DPUs) and ConnX DSP IP (intellectual property) cores. Tensilica is unique among IP suppliers as its Xtensa DPUs scale from very small micro cores to powerful 3-way VLIW DSPs ideal for power-efficient execution of Layer 2 and Layer 3 protocol stacks such as the solution from SySDSoft.

White Paper: Why High MHz Does Not Mean High Performance

Traditionally, performance has been associated with higher frequency. However, higher performance can be achieved even while running the processor at lower frequency. This leads to not only lower power, but also to better architecture-performance efficiency and lower area. This lower area in turn leads to even more power savings when compared to traditional deep-pipeline RISC processors. Read this white paper to find out more

Use Customizable Processors as SOC Building Blocks

General-purpose microprocessor cores can’t deliver the application throughput, cost, and power efficiency needed for most computationally demanding embedded SOC tasks. These processors aren’t designed to efficiently manipulate audio, video or network packets or do other highly specialized tasks.

Until now, these demanding tasks had to be hard coded in RTL to get the speed required. However, designing millions of gates in RTL takes too long, is too hard to verify, and can’t be changed once the chip is fabricated.

Now there’s a real alternative to RTL design. You can use configurable, extensible Xtensa processors instead of RTL to finish your design much faster and add flexibility to adapt to changing standards or product requirements. Tensilica’s Xtensa processors provide both the I/O throughput and the computational performance previously only available with RTL design.

Chelsio Communications licenses Tensilica's Xtensa processor

Chelsio Communications, Inc., of Sunnyvale, Calif., has licensed the Xtensa LX customizable DPU (dataplane processor) for its next-generation 10Gb Ethernet Terminator ASIC. Chelsio has used Tensilica's Xtensa DPUs in two previous generations of Terminator ASICs.

8 Years at Tensilica

Sometimes it's very hard to believe that I joined Tensilica 8 years ago last Saturday. I've seen a lot of growth in that time. Why do I stay? It's honestly a good job. We do a lot of creative things around here. I work with smart people. And the product is technically great.

Tensilica in Home Entertainment Systems

You can find Tensilica's cores in many home entertainment systems. We picked out 4 of the most interesting applications to give you more detail: Blu-ray Disc, set-top boxes, digital TVs, and digital radio.

New job posting: Baseband Biz Dev Mgr

We actually have 10 positions open at Tensilica now - we're really growing and investing in new areas, like Baseband where we've seen significant success with our ConnX BBE16 baseband DSP. If you know anyone good for this or any of the positions, let us know.

White Paper: Using Processors in the SOC Dataplane

To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines. Read this white paper for more info.

Arteris Adds Support for Tensilica's PIF for Network-on-Chip

This support will make it much easier for designers to get maximum efficiency when integrating Tensilica’s dataplane processing units (DPUs) into their system-on-chip designs. Using Arteris’ NoC technology, Tensilica’s DPUs can be mixed and matched with other processor cores or RTL blocks in complex, high-throughput designs. Tensilica’s DPUs are often used in multi-core chip designs, performing valuable data processing functions such as audio, video and baseband communications.

New FLAC Decoder for HiFi Audio DSP Core

FLAC - the Free Lossless Audio Codec - is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. Because it is not a proprietary format, is not encumbered by patents, and has an open-source reference implementation, FLAC has become increasingly popular. More information on FLAC is available at http://flac.sourceforge.net.

Eric Clapton Crossroads Concert

Yes, I'm lucky enough to go. So I'll be out of the office, returning Tuesday, 6/28.

New Job Post: Sr. Systems Network Administrator

Yes, we're hiring! The Sr. Systems and Network Administrator designs, analyzes, and implements projects for Cisco based LAN and/or WAN infrastructure. Additionally, this person analyzes, installs, and supports Windows operating system, database or utilities software. If you can do this, apply now!

Tensilica HiFi is first IP Core Approved for Dolby MS10 Multistream Decoder

The Dolby MS10 Multistream Decoder is critical to next-generation designs because it enables viewers to receive content not only from traditional broadcast and operator sources, but also from the Internet, USB devices, game consoles, and PCs. This array of source content uses a corresponding array of audio codecs, which Dolby has consolidated into MS10.

Build in Your Own Differentiation - Customize Your Processor Core

Your products will be harder for your competitors to copy, since you'll be using your unique processor instead of an industry standard core that anyone can purchase. And your products will be much more optimized for your application.

Company Picnic Today

Lots of fun things for kids and families. And the weather couldn't be better - nice and cool. Starts at 3.

Do you own an HP Laserjet printer with Tensilica processors inside?

Chances are, if you own an HP Laserjet, you have Tensilica product. We're also in Epson printers and printers from one major manufacturer that won't let us disclose their name. Why printers? For a while, the PC processor did most of the printing work. But with the shift to stand-alone printers that can be used as host=less printers for digital cameras, manufacturers had to build in a lot more processing power. And that's where Tensilica fits in. Our processors can be customized to do the tasks required, whether it's JPEG decompression, image enhancement, size scaling, color processor, or whatever.

Friday at #47DAC Workshop on SystemC with Analog, Digital, Software

In this tutorial, the presenters will cover the key concepts and state of the art methodologies for SystemC-based system development processes. A special emphasis is put on the interoperability of different domains, i.e., hardware, software, and analog. We will present an overview of the state of the art for a wide range of aspects including important topics such as executable specification, heterogeneous multi-processor SoC design, hardware-dependent software optimization, hardware/software co-verification, and analog, continuous-time system modeling. Industrial use cases will be used to illustrate the benefits from using and combining these methodologies based on SystemC’s ability to describe multi-domain systems. Featuring Tensilcia's Chief Scientist - Grant Martin.

On-Chip Communications: Where do we Stand Now?

Wednesday, June 16, 2010 - At the Design Automation Conference in Anaheim, CA
Time: 9:00 AM — 11:00 AM
Location: 209AB
It is around ten years since Networks-on-Chips emerged as an active research topic. There were widely varying opinions about the prospects for NOCs, ranging from "This is the future of on-chip interconnect" to "It will never work". The session will bring together prominent researchers and practitioners from the domain of on-chip communication architecture to look back at the decade of progress on this topic, and (i) evaluate where NOCs stand in terms of maturity as a research area, (ii) examine where they have succeeded and where they have failed, (iii) identify challenges and issues that remain to be addressed, and (iv) predict how they will be used in the next five years (Are they ready to replace buses as the mainstay architecture for on-chip interconnect? If not, where will NOCs thrive?). The session will conclude with a panel moderated by Grant Martin (Tensilica Chief Scientist) where speakers will speculate on the future of NOCs.

Tensilica- Berkeley Labs - Colorado Extraflop System Design

See how far researchers (and our CTO) have pushed multi-core Tensilica-based processing (20 million cores) to achieve incredible results. What a radical alternative - but it really makes sense.

Work in Our Cool Accounting Dept

Yes, we're growing and expanding and now need a senior accountant. Apply now. Accounting CAN be fun!

New VP: Eric Dewannain - VP/GM Baseband Business Unit

A very important addition to our Tensilica family, Eric has extensive experience at TI and Intel. "Because of our solid DPU foundation and success in baseband signal processing, we've been able to ramp up quickly and add top engineering talent to our team," stated Jack Guedj, Tensilica's president and CEO. "Now, with Eric, we're reaching critical mass with strong leadership to help us continue our growth trajectory."

"It's exciting to join an aggressive company that's rapidly becoming the architecture of choice for programmable baseband signal processing," Dewannain stated. "The amazing thing is how fast we can develop new products and provide optimized solutions for the mobile wireless market using the same Xtensa DPU foundation and tools we license to our customers. Leveraging this strong Xtensa DPU foundation, Tensilica has been able to develop a comprehensive IP (intellectual property) suite tailored for LTE and introduce two generations of ConnX BBE baseband DSPs in less than two years. Any other IP vendor would take several years to develop these products."

Updated White Paper: Diamond Standard Controllers

Need a good controller? Tensilica has the widest range of code-compatible controllers ranging from a very tiny, efficient basic controller (the Diamond 106Micro) to the super fast 3-way VLIW Diamond 570T. Check out this product line by looking at this white paper.

New Job Post: Design Verification Engineer - Santa Clara, CA

We now have 5 jobs posted:
- Design Verification Engineer - Santa Clara
- University Program Intern - Santa Clara
- Senior Application Engineer - Santa Clara
- Application Engineer - Pune, India
- Design Verification Engineer - Pune, India

Nintendo DSi - Cool Game with Tensilica Core Inside

Have fun playing with one of the coolest games with a Tensilica processor inside. The Nintendo DSi is just one example of all the great products that use Tensilica processors. Check out our customer gallery for more examples.

Updated White Paper on Audio DSP

This paper explains the benefits of using a programmable processor-based solution for audio processing in SOC designs, as well as the disadvantages of using a RISC or other general-purpose core. It explains the 300 audio-specific instructions added to make the HiFi 2 and HiFi EP Audio DSPs much more efficient than standard RISC processors to handle audio processing tasks.

Speeding Basic DSP Functions - FFT Example Ap Note

This is an introduction and tutorial to techniques applicable to accelerating the radix-2 FFT, using TIE techniques that are simple and easy to implement. This document discusses a basic, but very powerful capability of TIE, the ability to define a register file of any arbitrary width and instructions that perform computations on the register file. Additional techniques, such as FUSION and SIMD, are introduced to show how to further improve performance, along with techniques to reduce gate count. These TIE techniques improve FFT performance by a factor of almost 100 times compared to a conventional processor. While the radix-2 FFT algorithm was chosen to illustrate the use of TIE on a relatively simple DSP algorithm, the techniques covered in this application note apply to accelerating any algorithm.

Tensilica and Iberium Partner for DTV Solutions

"We entered into this partnership because we foresee a need to provide flexible, multi-standard IP solutions for the increasing number and complexity of worldwide DTV standards," stated Slobodan Simovich, Iberium's CEO. "Tensilica's DPU technology is a superior programmable platform that delivers performance and power efficiencies 10 to 100X greater than legacy CPU or DSP platforms."

New Job Post: Sr. Applications Engineer, Santa Clara, CA

Just posted this morning. If you know anyone, we're looking!

Now Hiring: University Program Intern

The University Program Intern is a 10-week summer position aimed at creating a University community that shares information on design projects and updating our University web presence.

RESPONSIBILITIES:
* Evaluate wealth of information we have on over 100 universities that have used Xtensa processors in their research.
* Determine an effective way to present and maintain that information online for (i) maximum interaction between universities and (ii) general industry awareness
* Implement the web presence as part of our existing website (CMS based)
* Determine how best to communicate with universities on a regular basis to maintain interest in our products and facilitate information exchange
Perform other duties as required in this dynamic business.
See our web site for full details. Email resumes to paula@tensilica.com

New Japan Office and Seminar on May 24

Our Japan office is celebrating its move to a larger office by hosting a customer seminar featuring discussions by representatives from NTT DOCOMO and Epson. If you're in Japan, be sure to sign up for our seminar.

Great article: Making IP Tradeoffs for Power

In this interesting article from Chip Design Magazine, the author interviews people from several IP companies, including Tensilica. The key to analyzing hardware design changes is to see what happens to the software once the change is made. That's the beauty of Tensilica's Xenergy tool. Change the processor, test out the software. See what changes make the most sense. Find out more about Xenergy at http://www.tensilica.com/products/literature-docs/application-notes/xtensa-tools/xenergy-energy-optimizator.htm.

Seminar in Japan May 24

Sign up now for our seminar in Yokohama, Japan on May 24. Representatives from NTT DOCOMO and Epson will discuss their use of Tensilica's technology.

Reflections on Cadence Acquisition of Denali

Today Cadence announced that they were acquiring Denali to help fulfill their EDA360 vision. Cadence is far behind Synopsys in providing the entire 360 design view. Way back in the early '90s Synopsys made a huge investment in their DesignWare products, which continues to this day (I was the director of corp. comm at Synopsys from '93-'96).

It's good to see Cadence executing on their vision. Maybe we should expect other acquisitions as well? Who's next?

Whitepaper: Exploiting Core's Law" Geting "More than Moore" productivity from your design

While it is feasible to build ASIC devices with more than 100 million transistors, designing these chips is a big challenge. Programmability vs efficiency trade-offs are examined, and suggestions are made for an improved ASIC design methodology using processors as basic building blocks.

HP LaserJet 1606ND Uses Tensilica's Processor

Following in a grand traditional of HP LaserJet printers based on Xtensa processors, the HP LaserJet 1606DN gets outstanding performance.

New ap note: Using TIE to accelerate Radix-2 FFT

This application note illustrates the acceleration of the radix-2 FFT, using TIE techniques that are simple and easy to implement. This document discusses a basic, but very powerful capability of TIE, the ability to define a register file of any arbitrary width and instructions that perform computations on the register file. Additional techniques, such as FUSION and SIMD, are introduced to show how to further improve performance, along with techniques to reduce gate count.

New Databooks Online

We've posted the databooks for Xtensa 8 and Xtensa LX3 online. Check out the latest features.

New Databooks Online

We've posted the databooks for our Xtensa 8 and Xtensa LX3 processors online now. Come check out the latest features.

Great article: 10 Reasons to Customize a Processor Core

See the article in Electronics Components World. Find out if you should consider customizing a processor core for your application.

New apnote: Using TIE Queues with Xtensa Processors

Want to see how easy it is to use Queues to bypass the bus altogether and get blazing fast data processing through the processor? Read this application note. Where the data is FIFO ordered, like audio samples or network packets, it makes sense to use RTL FIFO queues to manage the physical channel for the data. This note outlines the simple syntax to extend the Xtensa LX processor with input and output FIFO queue interfaces to couple tightly with external RTL FIFO queues

Need Screaming FFT Performance?

Try the ConnX Vectra LX DSP Engine. A basic Tensilica Xtensa LX processor might take 155,389 cycles for a 256pt Radix-4 FFT. But add Vectra LX, and that cycle count drops down to 994. Get performance, just where you need it.

Wolfson Licenses Tensilica's Hifi EP Audio

Goal: create a low-power, high definition sound platform. Combining Wolfson’s world-leading mixed-signal technology and audio expertise with Tensilica’s innovative HiFi audio digital signal processor (DSP) cores, this licence agreement will bring HD sound to multimedia platforms, including mobile handsets, netbooks, smartbooks, digital TVs and other multimedia devices.

With HD video a well-established standard in today’s consumer electronics world, this partnership will set the benchmark for HD sound and address consumer demand for crystal clear audio.

Resolving the Grand Paradox: Low Energy and Full Programmability in 4G Mobile Baseband SOCs

Click on the headline above to see Dr. Chris Rowen's presentation at the CoolChips conference in Yokohama, Japan (the presentation is in English) on April 15.

ConnX 545CK DSP Core Gets Faster, Smaller, Lower Power

Our third-generation ConnX 545CK 8-MAC VLIW DSP core for SOC designs delivers up to 20% faster clock speed, 11% smaller die area and up to 30% lower power consumption.

See our Product page as well and download the product brief.

Xtensa 8 or Xtensa LX3 - Which is Right for You?

Xtensa LX3 is a super-set of all Xtensa 8 features. But do you really need them all? Check out this page to see which one is best for your application.

Ultra-Low-Power Software-Defined Radio for LTE Wireless Baseband

See Dr. Chris Rowen's presentation to the IEEE Silicon Valley chapter meeting, where he discussed the embedded systems challenges to SDR.

Two Application Engineering Jobs Open - Plus More

We have an applications engineer job open in Santa Clara, CA, USA, and an audio specialist at our office in Pune, India. See our full list of job openings.

Free ThreadX Eval Download

Express Logic's popular ThreadX RTOS supports all of Tensilica's Diamond Standard and Xtensa configurable processor cores. The combination of ThreadX and Tensilica’s Xtensa is already production-proven in a high-volume SOC design used in personal laser printers.

ThreadX is a small-footprint RTOS with real-time determinism that enables Tensilica customers to support applications that demand high-performance, low overhead, and fast time-to-market. As a full port to all of the Tensilica products, ThreadX supports Tensilica’s onchip coprocessors including its floating point unit, Vectra DSP engine and special Tensilica Instruction Extension (TIE) cases. The simplicity and low cost of ThreadX, including its royalty-free licensing, make it attractive for high-volume applications in consumer devices, office automation, medical equipment and networking. ThreadX has been widely embraced and is currently deployed in over 300 million electronic products.

White Paper: A Designer’s Guide to HD Video Pre- and Post-Processing

HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.

Updated White Paper: Everything You Wanted to Know about SOC Memory

This paper discussed the many alternatives for on-chip and off-chip memory usage that SOC designer must understand. It discusses the essentials of memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory.

Using Multiple Processors in the SOC Dataplane

There are several advantages to using multiple processors as SOC task building blocks. One of the biggest is that processors are inherently programmable, so functional changes can be made to the chip’s operation using firmware after the chip design is finished and even after the chip has been fabricated. Complex state machines can be implemented in firmware running on the processors, greatly reducing verification time.

In addition, a multiple-processor-based design approach promotes the flexible sharing and reuse of on-chip memories while reducing the overall amount of memory needed.

Design with multiple processors facilitates system modeling with instruction-set simulators, which are much faster and more efficient than RTL-based system simulation. Read more about it here.

CTO Chris Rowen Speaking at CoolChips XIII in Yokohama, Japan

On Wednesday, April 14 at 10 am Dr. Rowen will discuss "Resolving the Grand Paradox: Low Energy and Full Programmability in 4G Mobile Baseband SOCs". On one hand, increased mobility dictates smaller batteries, longer battery life and improved energy efficiency. On the other hand, the complexity of new baseband standards like LTE - plus the multimedia, network protocols and application services enabled by fast baseband - dictate increased programmability, ubiquitous multi-core and more software layers. Rowen will describe practical successes for ultra-low energy processors used for LTE PHY subsystem designs achieving 150Mbps data rates in less than 250mW. And he will conclude that resolving this paradox has a domino effect on wireless infrastructure, DTV and wired communications.

Read BDTI's Independent Analysis of the Vectra LX DSP Engine

Tensilica's Vectra XL DSP engine is a quad-MAC DSP powerhouse. Once added to a base XTensa LX processor core with just a click of a configuration button, the Vectra LX DSP uses 64-bit instruction words containing 3 issue slots for ALU, multiply-accumulate, and load/store operations.

Like all configuration options, Vectra LX is fully supported by the entire Tensilica software environment including advanced auto-vectorization capabilities in the Xtensa C/C++ Compiler (XCC). XCC enables the Vectra LX engine designers to reap the benefits of vector processing on a SIMD engine without manual assembly level programming.

New Job Opening: Sr. Baseband System Archtiect - Santa Clara, CA USA

Know anyone good for this job? Our Baseband business is exploding because of the success of our ConnX Baseband Engine (BBE16). We want this success to continue. Here's part of the job description:

Key member of the baseband segment team for Tensilica working in the Office of the CTO. The baseband solutions architecture work with the overall baseband team to help define how Tensilica's DSP, multi-core and configurable processor technologies fits into wired and wireless communications systems designs, as well as defining and articulating the features and architectures required of next generation processor technology to serve the baseband segment.

White Paper: How to Avoid the Traps and Pitfalls of SOC Design

Chances are pretty good that your current SOC design approach is making your job much harder than it needs to be. Old bus-based architectures aren't efficient. Clock rates can't keep rising. What does work? Find out by reading this white paper.

Samsung Blu-ray Disc Player uses HiFi Audio

The Samsung BD-C6 900 3D Blu-ray Disc player uses Tensilica's HiFi Audio DSP. The player comes with support for 3D Blu-ray media playback at 1080p Full HD quality and has built-in support for WiFi connectivity. It can access the Internet@TV service and is BD-Live Ready. The BD-C6900 supports Dolby Digital , Dolby Digital Plus, Dolby TrueHD, DTS-HD and DTS-HD Master Audio Essential HD audio decoding, 7.1-channel output and 1080p DVD upscaling.

White Paper: Optimizing a DSP Architecture for Wireless Baseband

The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations.

The ConnX Baseband Engine is a configuration option package for Tensilca's Xtensa LX customizable processor core. It implements a 3-way VLIW, 8-way SIMD architecture that can sustain 16 multiply-add operations per second and performance of a full radix-4 FFT butterfly per cycle. At 400 MHz, it provides almost 13GM per second of memory bandwidth and 1.6B complex FIR filter taps per cycle. It directly implements 8-way parallel division and 4-way parallel reciprocal square root operations.  And up to eight ConnX Baseband Engines can be used together for maximum performance.

The rich programming environment, including vectorization of scalar C applications, allows easy deployment of into complex applications.  In addition, the Xtensa processor family, including the ConnX Baseband Engine, supports easy integration of multiple cores with high-bandwidth memory and direct port interconnect among each tightly-coupled cluster of cores.

The ConnX Baseband Engine is specifically designed for digital television, cellular basestation, femto-cell and other software-agile radio applications and is also being used to provide full programmability for  multi-standard broadcast receivers.

See Tensilica at SNUG - Synopsys Users Group

Tonight we'll be at the Vendor Fair and tomorrow afternoon we're in a tutorial "Extending Design Flows to the System-Level – How ESL Fits into Your Design Flow!" Click on the headline link to find out more about the tutorial session.

ConnX D2 Delivers Outstanding 16-bit Fixed Point DSP Performance on Compiled C Code

No need for assembly code optimization. This allows SOC development teams to have greater flexibility in resource allocation as well as the ability to quickly change algorithms. C code optimized with TI C6x or ITU C intrinsic functions compiles directly to the ConnX D2 instruction set, allowing developers to benefit from pre-existing TI and ITU code bases.

The ConnX D2 option adds dual 16-bit multiply-accumulate (MAC) units and a 40-bit register file to the base RISC architecture of the Xtensa LX processor. The ConnX D2 engine utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code. It also delivers dual-MAC performance using 64-bit VLIW (very long instruction word) instructions for code that cannot be vectorized.

White paper: Get your ASICs off the Bus

Bypass the bus altogether with GPIO and FIFO-like interfaces from Tensilica's processor cores. Read about how this significantly speeds data through the processor in this white paper.

See pics of NTT DOCOMO's demo at MWC of their LTE Platform

Tensilica's enabling next-generation LTE and 4G handsets. See pictures of NTT DOCOMO's demo at MEC of their LTE platform with multiple Tensilica Xtensa processors inside.

Diamond 570T - our Highest Performance Controller per EEMBC Benchmarks

It combines an efficient 5-stage pipeline with a 3-issue VLIW architecture, enabling it to obtain leading performance levels on both control and DSP code.

The Diamond 570T features innovative I/O that allows data to be streamed in and out of the processor without going over the main data bus. The two 32-wire GPIO (general-purpose I/O) ports allow direct control and monitoring of peripherals. Two 32-bit FIFO port interfaces can connect to standard FIFOs for direct, predictable communication with other RTL blocks, devices and processors.

IntegrIT Joins Tensilica’s Xtensions Partner Network for DSP Software Services

IntegrIT DSP Design House, a leading supplier of DSP software solutions, has joined Tensilica's Xtensions partner network to provide vital software components, including the high-performance Nature DSP Signal+ library, for the ConnX Baseband Engine, HiFi Audio DSPs and the ConnX D2 communications DSP.

The IntegrIT Nature DSP Signal+ is a collection of signal processing functions that assist the implementation of typical DSP algorithms. All functions are optimized for, and utilize, the full data bus bandwidth and computing power of each of the ConnX DSPs. The IntegrIT Nature DSP Signal+ library features over 30 common math and signal functions and is designed to be useful in practical real-time DSP applications.

Multiple Tensilica IP Cores Power NEC, Fujitsu and Panasonic Mobile Communications Fully Functional LTE Handset SOC

NTT DOCOMO has confirmed that several Tensilica Xtensa LX dataplane processor cores (DPUs) are used in the latest LTE (Long-Term Evolution) mobile handset system-on-chip design demonstrated in February at the Mobile World Congress (Barcelona, Spain). NTT DOCOMO previously exhibited the device developed under a collaborative project among DOCOMO, Fujitsu, NEC and Panasonic Mobile Communications (Panasonic Mobile), who will deploy the chip for their LTE handsets and datacards.

Spotlight on Diamond 106Micro - Our Smallest Controller

The Diamond Standard 106Micro CPU is a cache-less 32-bit controller ideal for designers looking for a basic 32-bit controller, particularly for those migrating up from an 8- or 16-bit controller. Designed for applications with requirements for minimal size and low power, the Diamond Standard 106Micro controller enables SOC architects to quickly integrate this efficient CPU in their designs.

Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline so it can achieve 650 MHz in 65gp process and up to 900 MHz in 45gs process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves much higher code density than other 32/16-bit architectures.

CTO Chris Rowen Speaking at Silicon Valley IEEE SSCS

Dr. Rowen will be talking about "Ultra-Low-Power Software-Defined Radio for LTE Wireless Baseband" at the Silicon Valley IEEE Solid State Circuits meeting this Thursday, March 18. Meeting open to everyone.

New 3rd Gen Diamond Controllers

This family of five upward-compatible processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today's compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption.

Why Designers Need a New DSP for SOC Designs

The rapid changes in wireline and wireless communications, disk drives, home entertainment devices, and computer peripherals are driving demand for 16-bit fixed-point DSPs. Stand-alone DSP chips are no longer cost effective for most of these price-sensitive applications. Instead, there's growing demand for general-purpose 16-bit DSP engines that can be easily designed into highly integrated SOC silicon.

At the same time, the growth of multiple standards and the complexity of these standards is driving developers away from traditional assembly-code programmed DSPs towards integrated architectures that combine excellent DSP performance with generalized high performance when developing with compiled native C control code.

The market needs a DSP engine that can easily be customized if necessary, integrated into a SOC design, and programmed most often in C, rather than assembly code. This will help speed new products to market as quickly as possible.

There's a Great Way Around the Slow Processor Bus

Read our white paper to learn how you can bypass the bus using our ports (like GPIOs) and queues (like FIFOs) to directly connect processors, much like you would connect RTL blocks.

Congratulations Cisco on Your CRS-3 Announcement

When Cisco needs to design chips for their fastest routers, they've turned to Tensilica's cores. We're delighted to see that, once again, Cisco is pushing the envelope and developing the next generation network infrastructure products that we definitely need.

Match Processor to Task by Automatically Generating the Processor Core

Read our white paper. You can use our XPRES Compiler to analyze your C code algorithm and suggest the processor changes that will accelerate that algorithm. Then, when you've optimized your processor, Tensilica will automatically generate the matching software tools that take advantage of all of your optimizations. Nice.

CTO Chris Rowen Speaking at DATE Conference Next Week

DATE is March 8-12, 2010, in Dresden, Germany. Dr. Rowen is speaking at 3 sessions:

Session 7.1 "Fabulous, Frightening and True: Stories of Multicore SOC Design for Wireless Baseband", Wed. 3/10/2010 14:30-16:00.

Panel 2.8 "Are we there yet? Has system assembly from IP blocks become like connecting LEGO blocks?", Tue., 3/09/10 11:30-13:00

Panel 10.8 "Embedded Software Testing: What Kind of Problem is This?", Thu. 3/11/10 8:30-10:00

FFT Ap Note

This ap note shows the results and design methodology for a high-performance DSP sample application on the Xtensa microprocessor using a widely known example, the Fast Fourier Transform (FFT). This note first explains the basic algorithm and how several TIE language instructions were created to implement the FFT algorithm. Performance results follow, with a comparison of implementations of the radix-2 decimation-in-frequency FFT with and without additional TIE language extensions.

Fast OFDM Ap Note

This application note looks briefly at fast signal processing for wireless modems. In particular, this application note describes the TIE (Tensilica Instruction Extension) language instructions that accelerate the complex FFT and FIR operations that dominate many OFDM channel modulation and demodulation systems.

Why High MHz Doesn't Necessarily Mean High Performance

Read our white paper. Traditionally, performance has been associated with higher frequency. However, higher performance can be achieved even while running the processor at lower frequency. This leads to not only lower power, but also to better architecture-performance efficiency and lower area. This lower area in turn leads to even more power savings when compared to traditional deep-pipeline RISC processors.

How to do multicore design the right way?

Check out our web section on some of the things you must consider when doing multicore design. Most of our customers do multicore design because one core just can't do everything. Specialized cores for the dataplane are the answer.

Smartphone (ARM) or Netbook (Intel)? You'll find Tensilica in Both

Fore very one applications processor (ARM or Intel) there are tens or hundreds of other processors doing the baseband DSP, audio, video, graphics, security, biometrics, WiFi, GPS, and much more. And that's where you'll find Tensilica's dataplane processors (DPUs).

WW Sales Conference This Week

I'm really looking forward to today's updates from the sales team. Tomorrow's marketing's turn to present new product plans and strategies. I'm on the schedule to discuss our next seminar program among other exciting things. This year looks much better than last at this point in time. Last year turned out great, but it was pretty dismal in February. New design activity has picked up worldwide.

Saluting partner HiFi Audio Partner Dolby Labs

Tensilica offers the most complete set of fully qualified decoders for Dolby's fantastic audio products, including Dolby TrueHD, for Tensilica's HiFi 2 and HiFi EP Audio DSPs.

Mobile World Congress Booth Was Packed - see the pic

Yes, this is our booth at the MWC in Barcelona. It was packed! Great show for Tensilica. Lots of important meetings and an opportunity to meet a lot of new people with creative ideas for next-generation smart phones. Our ConnX Baseband Engine and demo with mimoOn was a particular draw for the crowds. Sometimes it was hard to clearly hear the audio demos because it was so busy.

New Job Opening: Applications Engineer, Santa Clara

You will be a member of the applications engineering team at Tensilica, with a focus on software development for Xtensa processors and usage of Xtensa software tools. The applications engineering team is responsible for the worldwide support of Tensilica customers, helping them use and integrate our microprocessor cores in their SoCs and develop software for these microprocessor cores. The team is also responsible for training customers on our tools and technologies, authoring application notes and other collateral that helps customers make effective use of our products.

Thinking 4G? Read our whitepaper: The 5 Pitfalls of 4G Baseband SOC Design

As Tensilica has been working with its customers to design building blocks for LTE PHY designs, including the DSPs and forward-error-correction subsystems, we've realized five key pitfalls associated with LTE baseband development.

See Tensilica at Mobile World Congress Booth 7C35

Last call for private meetings. See our new ConnX BBE16 Baseband Engine, the ConnX Atlas Reference Architecture, and - of course - our new HiFi EP and video in action.

New Product Brief on BBE16 - Baseband Engine for LTE

Find out the inside story by reading the product brief.

Xtensions Partner Program Expands for LTE/4G Design

Tensilica's Xtensions Partner Program brings its LTE baseband handset and base station design customers a robust infrastructure of top-tier partners in SOC (system-on-chip) design-critical areas such as LTE physical layer software solutions, system level modeling, real time operating systems emulation, and design services.

New Partner: mimoOn for LTE handset software

Partnership with mimoOn offers best-in-class LTE solutions for mobile wireless radios based on mimoOn's mi!MobilePHY software and Tensilica's newly announced ConnX Baseband Engine (BBE16) and ConnX Atlas LTE Reference Architecture.

HiSilicon, a division of Huawei, Licenses Tensilica's Xtensa Dataplane Processors and ConnX DSPs

HiSilicon will use Tensilica's DPUs and DSPs in network equipment chip design.

"We conducted a thorough review and evaluation of licensable DSP IP cores before selecting Tensilica," stated Teresa He, Vice President of HiSilicon. "Tensilica's unique ability to combine world-class DSP capability with the flexibility and customization of the Xtensa DPUs gives HiSilicon the opportunity to strongly differentiate our products. We feel this will give us a strong competitive advantage."

New ReferenceArchitecture for LTE Designs

The ConnX Atlas LTE (Long-Term Evolution) reference platform is a heterogeneous seven-core reference architecture for a complete multi-standard programmable radio for advanced mobile devices. Atlas is designed to support the 3GPP LTE standard, as well as other complementary standards such as HSPA+, in a single platform. No additional hardwired hardware blocks are required, even for the computationally complex turbo decoder at 154 Mbps downstream data rates.

Second Generation ConnX BaseBand Engine DSP for Demanding Algorithms for LTE/4G Wireless Handsets and Base Stations

ConnX BBE's 16-way MAC architecture is optimized for the most demanding wireless DSP tasks, including ODFM, FFT, FIR, IIR, and matrix computations. We introduced the first BBE in June of 2009. Tensilica has licensed ConnX BBE to several customers and it is already in volume production. Based on customer feedback, Tensilica developed its next generation DSP: the ConnX BBE16. ConnX BBE16 was developed in record time, leveraging the Tensilica Xtensa® customizable processor foundation technology.

Monday, Monday, Monday

I've been very busy (and will be working this weekend) getting ready for Monday's big announcements - another LTE solution coming right up!

Specs for HiFi EP Running DTS Master Audio

Just loaded on our web site the performance data on all of the DTS applications, including the incredibly demanding DTS Master Audio. With HiFi EP, single-core Blu-ray Disc SOCs can easily be implemented in 65GP with additional MHz to spare for other audio functions.

New HiiFi EP Reduces MHz Requirement for DTS Master Audio

HiFi EP's architectural enhancements significantly improve DTS Master Audio decoding and tolerance to high external memory latency. With HiFi EP, single-core Blu-ray Disc SOCs can easily be implemented in 65GP with additional MHz to spare for other audio functions. See the mHz savings.

New HiFi EP for Home Entertainment and Smartphones

Building on the success of its HiFi 2 Audio DSP, the leading architecture for audio in SOC designs, Tensilica today introduced HiFi EP, a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre and post processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. It has also been enhanced for very efficient, high-quality voice pre-and post-processing. These enhancements result in up to 40 percent lower power and up to a 50 percent size reduction. Tensilica will be demonstrating its HiFi EP Audio DSP (digital signal processing) Engine in booth 7C35 at the Mobile World Congress, February 15-18, 2010 in Barcelona, Spain.

Web site down at 5 pm PDT

We're switching over to a new ISP at 5 pm and it should only take a few minutes. It might take a while for the switch to populate through all the routers in the world. Let's all hope it happens quickly!

Almost Ready for Monday's Audio Announcement

What's next for our highly successful audio product line? Tune in Monday.

See Tensilica at Mobile World Congress Booth 7C35

We're setting up appointments now. Lots of good things will be introduced in the next 2 weeks - you'll want to see them up front and in person if you're going to the show. To set up an appointment, email paula@tensilica.com.

2 New Job Openings in Pune, India

Two DSP engineering jobs open at our Pune facility: One for Audio DSP and one for Baseband Comms DSP.

Hiring: Aps Engineer - Baseband DSP

Yes, Tensilica is hiring. We currently have four open positions listed on our Careers web page (click headline above). One is for an Applications Engineer for Baseband DSP. Know anyone good?

Tensilica's all over mobile handsets

Security, decryption, imaging, video, audio, baseband PHY and MAC, fingerprint processing - see all the places Tensilica processors are found in handsets.

See how easy it is to configure a processor

Watch the video. See Chris Rowen explain how easy it is to configure a processor using Tensilica's automated system.

WhitePaper: 5 Pitfalls of 4G Baseband SOC Design

As Tensilica has been working with its customers to design building blocks for LTE PHY designs, including the DSPs and forward-error-correction subsystems, we've realized five key pitfalls associated with LTE baseband development. See this brand new white paper for more details.

Job Opening - Sr. Compiler Engineer

As a member of the software development tools team, you will participate in the design and implementation of the Tensilica software toolchain, in particular the C/C++ compiler targeted for Xtensa processors. Your responsibilities will include maintaining and improving existing compiler algorithms, as well as working closely with software, hardware and application teams on specifying and developing new features.

Google Nexus One - Tensilica Inside

Just got my Google Nexus One. Actually, I wish it were really mine - it belongs to Tensilica and we'll be taking it to Mobile World Congress next month to show it off. We're proud to say that a Tensilica processor is inside this phone!

New Book: ESL Models and Their Applications

Edited by Tensilica Chief Scientist Grant Martin and Brian Bailey, this book provides insight into all phases of ESL model design. Especially Chapter 6: Processor-Centric Design:L Processors, Multiprocessors, Software.

White Paper: A Designer’s Guide to HD Video Pre- and Post-Processing

HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.

Microprocessor Report Calls Tensilica's Configurable Processor Tech the Best

Read this review of our Xtensa 8 and LX3 cores from Microprocessor Report.

AMD's New Radeon HD 5870 - Tensilica Inside

World's first mobile graphics with Microsoft DirectX 11 gaming support for notebook computers was announced at CES - and Tensilica is inside every one of them! Tensilica's processors configured to accelerate video stream decoding are an ingredient in every UVD-powered AMD ATI graphics chip, including those with ATI Avivo HD video and display technology, which provdes PC users with crisp images, smooth videos and true-to-life colors.

Tensilica demonstrates success in audio and baseband DSP at CES

A host of products based on Tensilica's dataplane processors (DPUs) will be demonstrated at this year's Consumer Electronics Show, January 7-10 in Las Vegas. These Tensilica-enabled products include some of the most advanced, innovative consumer devices, including Blu-ray Disc players, Bluetooth-enabled devices, LCD TVs, cellular phones, WiFi- and W-USB-enabled notebook computers, wireless HDMI, handheld games, and inkjet and laser printers. Tensilica will showcase its leading-edge audio, video and baseband communication IP cores, including the popular HiFi 2 Audio Engine running on the Android platform in collaboration with MIPS Technologies, in the South Hall of the Las Vegas Convention Center, suite South 4 35567MP.

Back to Basics: Using Processors in the SOC Dataplane

Read the whitepaper. Designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines.