Friday, May 21, 2010
New Job Post: Sr. Applications Engineer, Santa Clara, CA
Just posted this morning. If you know anyone, we're looking!
skip to main |
skip to sidebar
All the news you're looking for from Tensilica, Inc. Find out how you can use Tensilica's customizable, extensible processors to speed your SOC design. See Tensilica for DSPs and all the processing you need to do in the dataplane (dataplane processors - DPUs).
Follow us on:
Followers
Blog Archive
-
▼
2010
(166)
-
▼
May
(16)
- Speeding Basic DSP Functions - FFT Example Ap Note
- Tensilica and Iberium Partner for DTV Solutions
- New Job Post: Sr. Applications Engineer, Santa Cla...
- Now Hiring: University Program Intern
- New Japan Office and Seminar on May 24
- Great article: Making IP Tradeoffs for Power
- Seminar in Japan May 24
- Reflections on Cadence Acquisition of Denali
- Whitepaper: Exploiting Core's Law" Geting "More th...
- HP LaserJet 1606ND Uses Tensilica's Processor
- New ap note: Using TIE to accelerate Radix-2 FFT
- New Databooks Online
- New Databooks Online
- Great article: 10 Reasons to Customize a Processor...
- New apnote: Using TIE Queues with Xtensa Processors
- Need Screaming FFT Performance?
-
▼
May
(16)
Links - Web Sites
About Me
- Tensilica
- I'm the director of corporate communications at Tensilica. I really believe in our technology and just want to show engineers just how productive they can be with our automated tools.