Tuesday, December 19, 2006
According to EDN, “Built by and for electronics engineers, this list distills the most innovative and significant products of the year, including process technologies, power sources, processor cores, communication controllers, test instruments, embedded boards, EDA tools, and more.
“Our editors mercilessly cull the herd of new-product announcements they see during the year, resulting in this distillation of the most innovative and significant offerings,” EDN added.
EDN’s Top 100 list can be viewed at http://www.edn.com/article/CA6399100.html.
Madhu Parthasarathy, general manager, DSP & Multimedia Applications, Wipro Technologies, said, “Our advanced algorithm group has been actively evaluating processors to address the low-cost, enhanced computing requirements of applications in the biometric space, such as fingerprint recognition/matching. The Tensilica Diamond processor series meet the requirements and also offers the added advantage of a logically scalable path to extend our algorithms to a wider range of applications that our HW-SW architecture group and the HW acceleration service lines view as essential to cater to the complex SOC requirements in the future.”
Friday, December 15, 2006
The Diamond Standard VDO engines host all the key video processing functions in software on the cores – including the network abstraction layer, picture layer, slice layer, bit-stream parsing and entropy decoding and encoding. This includes the computationally demanding CABAC (Context Adaptive Binary Arithmetic Coding) decoding in the H.264 Main profile decoder that most other solutions omit, implement in a separate and complex non-programmable hardware block or necessitate more than 700 MHz of general CPU workload which significantly increases power consumption. By implementing CABAC in instruction set extensions, Tensilica was able to create a low MHz and power efficient version of CABAC in less than half the area of a typical CABAC hardware block.
The Diamond VDO family offers both Baseline and Main profile solutions – Main profile offers superior data compression and video quality and is the preferred coding scheme at resolutions of D1 and higher for advanced handset and PMP applications. Most other video solutions for SOC design only implement Baseline profile video.
Both processors feature several architectural enhancements, and are the first configurable licensable core families available with built-in, on-the-fly Error Correcting Code (ECC), which is extremely important in storage, networking, automotive and transaction processing applications where data integrity and error resiliency are of paramount concern. Tensilica’s new generation of processors reinforce Tensilica’s processor technology leadership by remaining the lowest power, highest performance licensable cores on the market. Both processors are available and shipping now.
See http://www.tensilica.com/news_events/pr_2006_12_04LX2.htm for highlights of what's new in these two processors.
Friday, December 01, 2006
“Over the past year, we’ve seen increasing demand for our products on both families of Tensilica processors – the Diamond Standard series and the Xtensa configurable processors – as more designers are using these products in their SoC designs,” stated Norbert Weiss, International sales manager from Lauterbach. “Tensilica’s processors are particularly popular in multicore designs, which we service very well with our TRACE32-ICD.”
The PowerDebug (in-circuit debugger) is a high-performance JTAG debugger. The PowerDebug’s hardware consists of a universal debug module that can be connected to any PC or workstation via a USB 2.x or Ethernet interface. The PowerView software supports multicore debugging. Graphical variable displays and dedicated commands to handle large arrays support the development of DSP-specific code. The combination of the debugger and the PowerProbe logic analyzer enables real-time measurements. The PowerView debugger software provides a unified, graphical environment for debugging SoCs with one or more Tensilica processors, or a combination of Tensilica processors plus cores from other vendors in a heterogeneous debug environment.
Wednesday, November 08, 2006
The two tunes available, “Les is Moore” and “Pigsaw Juzzle,” are from the Pigsaw Juzzle CD from the Hip Pocket Jazz Quintet (http://hippocket.jazzcombo.com). The Hip Pocket Jazz Quintet has been playing in the San Francisco Bay Area since 1989 and Pigsaw Juzzle marks the group's first all-original release. The cornerstone of Hip Pocket's philosophy is to create truly improvised jazz. All the musicians are in the same room at the same time and there are no overdubs.
Wednesday, November 01, 2006
For more information on the HiFi 2 audio engine, see http://www.tensilica.com/products/hifi_audio.htm
For more information on the Diamond Standard 330HiFi Audio processor, see http://www.tensilica.com/diamond/di_330hifi.htm
Wednesday, October 25, 2006
Tuesday, 8 am - "MPSOC Flow for Multiformat Video Decoder based on Configurable and Extensible Processors" – Gulbin Ezer
Wednesday, 11 am - "Integrating IP in Multicore DSP/Processor SoCs "- panel on Multicore SOC design – Sumit Gupta
Thursday, 8 am - "Goodbye, Mr. DSP: DSP IP Cores are Superfluous for New SOC Designs" – Steve Leibson
“We selected Tensilica’s Xtensa processors because of the ease with which we were able to optimize certain functions for our high-speed, demanding Ethernet channel adapters,” stated Rick Maule, NetEffect’s CEO. “Tensilica’s automated process let us optimize our embedded processors for our exact application in a fraction of the time that it would have taken us using other alternatives.”
For more info, see http://www.tensilica.com/news_events/pr_2006_10_24.htm
Thursday, October 19, 2006
"Tensilica’s Xtensa processor was very attractive for our next design because standard processor cores couldn’t give us the performance we needed,” stated Hamilton Yong, COO, NuFront Software. “The only way to get the performance was to be able to optimize the processor, and Tensilica is the only company with the automated tools to make that customization much easier and ensure our success.”
Wednesday, October 18, 2006
"Tensilica’s Diamond Standard 108Mini core perfectly met our needs for a low-cost, low-power, high-performance controller core for a high-volume customer application in the mobile space,” stated Jim Su, chief executive officer of EES. “We evaluated all of the popular 32-bit controller cores on the market, and Tensilica’s Diamond Standard 108Mini gave us the best price,performance and power solution.”
Tuesday, October 10, 2006
“We picked Tensilica’s Xtensa processor because we were very impressed with the ability to customize it, using the TIE (Tensilica Instruction Extension) language, for our demanding mobile TV demodulator application,” stated Philip Sun, Afa’s executive vice president. “Tensilica’s unique technology allows us to implement in low-power processors what previously was only possible using hardwired logic. By optimizing the Xtensa processor, we can deliver a programmable solution for advanced mobile TV handsets, and still meet the low power constraints needed to deliver the long battery life consumers expect.”
For more information, see http://www.tensilica.com/news_events/pr_2006_10_10.htm
Wednesday, October 04, 2006
“We picked Tensilica’s Diamond 108Mini over other processor cores because of the small code size, small area and ease of integration into our product development environment,” said Murty Bhavana, Nethra’s vice president of marketing. "Image and video capture and processing require very high performance imaging algorithms. Using a Diamond 108Mini to provide a high performance processor core, our customers will have enough headroom to add their IP and provide product differentiation."
For more information, see http://www.tensilica.com/news_events/pr_2006_10_03.htm
Tuesday, September 26, 2006
ThreadX is a small-footprint RTOS with real-time determinism that enables Tensilica customers to support applications that demand high-performance, low overhead, and fast time-to-market. As a full port to all of the Tensilica products, ThreadX supports Tensilica’s on-chip coprocessors including its floating point unit, Vectra DSP engine and special Tensilica Instruction Extension (TIE) cases. The simplicity and low cost of ThreadX, including its royalty-free licensing, make it attractive for high-volume applications in consumer devices, office automation, medical equipment and networking. ThreadX has been widely embraced and is currently deployed in over 300 million electronic products.
For more info, see http://www.tensilica.com/partners/os_express_logic.htm
Monday, September 25, 2006
“We are working with Tensilica because a growing number of design teams are using Tensilica’s Diamond Standard processor cores,” stated Heiko Mauersberger, ProDesign’s chief technology officer. “The Diamond Standard cores deliver the best mix of low power and high performance for applications ranging from simple 32-bit controllers to high-end DSPs and an audio processor.”
ProDesign’s CHIPit ASIC Prototyping line provides an integrated set of tools with debug capabilities that provide a dual solution for hardware and software verification and validation throughout the product life cycle. The FPGA-based ProDesign CHIPit platforms can handle capacities up to 21-million ASIC gates and run at system speeds up to 200 MHz.
For more info, see http://www.tensilica.com/partners/hw_prodesign.htm
Friday, September 22, 2006
“Our Diamond Standard processors have been prototyped and verified with great success on HAPS products by several of our customers and partners,” stated Larry Przywara, Tensilica’s director of strategic alliances. “Our customers appreciate the flexibility and cost-effectiveness that the highly modular HAPS products provide. HARDI is a solid platform for verifying multi-million gate ASIC designs.”
“HAPS is the ideal platform for customers of Tensilica’s popular Diamond Standard processors to use to prototype and verify their ASIC designs, as well as get a head start in generating embedded software,” stated Lars-Eric Lundgren, president of HARDI Electronics. “The HAPS system can scale from small projects to providing industry leading capacity for large ASIC designs, so it is suitable for any Diamond processor-based SOC prototype.”
Tuesday, September 19, 2006
“We’re seeing an increased demand for Tensilica’s Xtensa and Diamond Standard processors in a wide variety of applications from current and potential new customers,” stated eInfochips VP of marketing Tapan Joshi. “Our expertise can help these customers get their new designs to market much faster. And we can provide the full range of services for Tensilica customers, from silicon design and verification to embedded firmware development and total system integration.”
See http://www.tensilica.com/news_events/pr_2006_09_19.htm for more information
Monday, September 18, 2006
iBiquity is the sole developer of digital HD Radio technology, providing the innovations that allow the transmission of digital audio and data along with existing AM and FM analog signals. Besides delivering vastly superior sound that virtually eliminates the static and hiss often associated with analog radio, iBiquity’s technology provides a platform for advanced new services including HD2 multicasting, enabling FM stations to broadcast multiple streams of unique programming over a single frequency. More than 3,000 stations in the U.S. are in the process of upgrading to iBiquity’s digital HD Radio technology, with nearly 1,000 on the air and approximately 350 offering HD2 multicast channels. In addition, the technology is gaining visibility throughout the world.
“We chose Tensilica’s configurable processor technology because it provided a common processor platform that could be optimized for both the digital baseband and audio portions of our design,” stated Gene Parrella, iBiquity’s vice president of IC Development. “We were also very impressed with Tensilica’s area and power efficient processor technology. Both silicon area efficiency and low-power for portability are essential for our customers.”
Friday, September 15, 2006
Tuesday, September 12, 2006
The processors range from a low-power 32-bit controller up to the industry’s highest performance digital signal processing (DSP) core and a multifunction audio processor that has been designed into millions of cellular phones. Under the agreement, Tensilica’s Diamond Standard processors will be available to Fujitsu’s ASIC customers via the company’s IPWare library and COT customer directly.
“Tensilica’s Diamond Standard processor family includes controllers for the entire range of design requirements, so our customers can select the version that is optimal for their ASIC and COT design,” said Jason So, senior director of COT and ASIC Business Group for Fujitsu Microelectronics America. “We are pleased to offer the processor family as part of our extensive portfolio of solutions.”
Monday, September 11, 2006
Mentor Graphics Seamless product has been named the premier co-verification tool for Tensilicas new Diamond Standard series of processor cores. Seamless provides designers with a virtual platform to debug hardware/software integration issues while increasing simulation throughput, thereby allowing designers to quickly validate that the system hardware and software are functionally correct before prototypes are manufactured.
This online seminar walks you through the basics of these two product lines, explaining how they work in conjunction with one another to provide a complete solution to SoC design complexity.
Wednesday, September 06, 2006
Tuesday, August 22, 2006
Friday, July 28, 2006
“For the customer who just wants a drop-in solution for fast deployment late in the design cycle, the Diamond Standard processors hit the market’s sweet spots,” stated Chris Rowen, Tensilica’s president and CEO. “The typical processor customer wants standard control or DSP functions in the smallest, most power-efficient form factor – and that’s what we have to offer. We’re particularly pleased that our Diamond Standard processor family opened up doors at new customer sites, expanding our reach in the SOC design community.”
More at: http://www.tensilica.com/news_events/pr_2006_07_18.htm
Thursday, July 13, 2006
"Every chip designer is, in many ways, an artist. So at DAC, we’re celebrating the artist within each of us by letting attendees paint parts of giant pictures that tell the story of chip design,” stated Chris Rowen, Tensilica’s president and CEO. “We’ll use this artwork to support another art – ballet. Ballet San Jose is an integral part of our Silicon Valley culture and deserves widespread support.”
During the 4-day DAC exhibition, attendees will be able to paint part of a different picture each day. To preview the pictures and find out more, see http://www.tensilica.com/company/DAC_2006.htm
The book, published by Morgan Kaufmann, provides SOC designers with a practical introduction to three basic techniques of modern SOC design: use of optimized standard CPU and DSP processors cores, application-specific configuration of processor cores, and system-level design of SOCs using configured cores as the key building block. The book has a list price of $59.95 and is available at www.books.elsevier.com.
Thursday, June 29, 2006
For more information, see: http://www.tensilica.com/news_events/pr_2006_06_27.htm
Monday, June 26, 2006
Silistix Partners with Tensilica to Develop a Demonstration Test Chip for Portable Multimedia Applications
Thursday, June 22, 2006
Read more about what Greg Christison had to say at:
Wednesday, May 31, 2006
"Tensilica’s automated configurable processor design approach gives us the speed we need with lower power and smaller die size,” stated Dennis Shwed, Neterion’s vice president of hardware engineering. “Tensilica’s Xtensa LX processor delivers the performance levels required for demanding 10-gigabit Ethernet in high-speed server and storage networking applications.”
For more information, see http://www.tensilica.com/news_events/pr_2006_05_31.htm
Tuesday, May 30, 2006
Tuesday, May 23, 2006
“In all, Tensilica’s 10 patents make nearly 450 claims of inventions in the rapidly evolving field of configurable-processor technology,” stated Tom Halfhill, senior analyst for In-Stat’s Microprocessor Report. “Although judging the strength of a patent portfolio by counting claims is like measuring microprocessor performance by counting megahertz, the large number of claims does indicate that Tensilica is staking out a great deal of territory.”
For more information, see http://www.tensilica.com/news_events/pr_2006_05_22new.htm
“The challenge has largely backfired,” stated Tom Halfhill, senior analyst for In-Stat’s Microprocessor Report. “The anonymous challenge has almost certainly strengthened this key patent. Having survived a lengthy reexamination and emerging with almost twice as many claims, it is unlikely to be challenged again.”
Wednesday, April 19, 2006
"We liked Tensilica’s Diamond 108Mini because it gave us the performance we needed in a small form factor,” stated Ramin Shirani, vice president of engineering, Aquantia. “With its small footprint and minimal power requirements, the Diamond 108Mini is well suited for general control applications."
For more information, see http://www.tensilica.com/news_events/pr_2006_04_19.htm
"We particularly liked the in-bound DMA capability of the Diamond Standard series,” stated Moshe Steiner, CEO, Lucid. “With this feature we are able to realize significantly higher computational and data throughput when compared to alternative architectures."
For more information, see http://www.tensilica.com/news_events/pr_2006_04_18.htm
Monday, April 17, 2006
Wednesday, March 15, 2006
Software and firmware engineers will want to explore the Diamond processor software development tools to learn how easy it is to port application code to the Diamond core processor family, and to experience the code performance and code size advantages of the Tensilica Xtensa instruction set architecture. Powerful visualization tools enable software developers to graphically view and compare profiling results.
Hardware design teams will want to take advantage of this free evaluation to experiment with the clock-cycle accurate, pipeline-modeling instruction set simulator and the associated performance modeling visualization views within the graphical user interface that show pipeline activity, cache utilization rates, and cycles spent on bus cycle activity.
Monday, March 13, 2006
Tensilica and CSIP of Ministry of Information Industry (MII) of PRC Establish First Joint IP Core Lab
“It is our great honor to be the first company to set up an IP core lab with CSIP,” stated Chris Rowen, Tensilica president and CEO. “We will strive to provide world leading processor technology for Chinese clients through this lab so as to accelerate China’s SOC design and create more ICs with independent IP.”
For more information, visit http://www.tensilica.com/news_events/pr_2006_02_23.htm
This announcement provides Tensilica with the broadest range of off-the-shelf processors in the industry, with the six Diamond Standard cores plus an almost infinite number of processor configuration possibilities for those customers requiring optimized, application-specific processors with Tensilica’s award-winning Xtensa configurable processor family.
For a full list of all Diamond press releases, see http://www.tensilica.com/news_events/press_releases_2006.htm.
Saturday, February 11, 2006
Sunday, February 05, 2006
“We selected the Tensilica Xtensa processor because they offered us the most flexibility and achieved the lowest power for a programmable solution,” stated Greg Winner, COO of u-Nav Microelectronics. “With the ability to customize Xtensa through Tensilica’s automated processor generation technology, and the inclusion of u-Nav’s custom instructions, we created a unique way to significantly lower the total power consumption of our complete GPS system-on-chip design.”
For more, see http://www.tensilica.com/news_events/pr_2006_02_06.htm.
Thursday, January 26, 2006
MediaWorks employs Xtensa processors in their recently announced groundbreaking MediaFlex™ platform architecture and MW301 Media Processor. See http://www.tensilica.com/news_events/pr_2006_01_25.htm
for more information.
Olympus is making its Tensilica license, which now has been expanded to include Xtensa LX, available to its design groups in its Corporate R&D Center in both Japan and the United States. See
for more information.