Using Multiple Processors in the SOC Dataplane

There are several advantages to using multiple processors as SOC task building blocks. One of the biggest is that processors are inherently programmable, so functional changes can be made to the chip’s operation using firmware after the chip design is finished and even after the chip has been fabricated. Complex state machines can be implemented in firmware running on the processors, greatly reducing verification time.

In addition, a multiple-processor-based design approach promotes the flexible sharing and reuse of on-chip memories while reducing the overall amount of memory needed.

Design with multiple processors facilitates system modeling with instruction-set simulators, which are much faster and more efficient than RTL-based system simulation. Read more about it here.