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Wednesday, January 31, 2007

Tensilica Adds G.729AB Speech Codec for HiFi 2 Audio Engine

Tensilica introduced another codec for its popular HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core which are specifically optimized for audio in mobile multimedia devices. The G.729AB speech codec, mostly used in Voice over IP (VoIP) applications, is fully compliant with ITU (International Telecommunication Union) specifications for the G.729 standard with annexes A and B. As an ITU standard, G.729 is one of the most tested and lowest bandwidth digital speech transmission standards.

For more information, see

Tuesday, January 30, 2007

Epson Licenses Xtensa LX for Printer Designs

Seiko Epson Corporation (“Epson”) has closed a long-term, multi-year license of Tensilica’s Xtensa family of configurable processor cores for Epson’s new REALOID printer engine chip. The first generation REALOID chip is used in Epson’s latest photo-capable inkjet printers and multi-function printers (MFPs), including the newly announced Colorio PM series MFPs. The Epson Stylus Photo R380 Ultra High-Definition REALOID-based printer is now available in the US. The strategic relationship also includes next-generation REALOID designs.

Epson’s engineers added Tensilica Instruction Extensions (TIE ) to customize several different Xtensa LX processors, each for a unique step in the inkjet image processing chain. By utilizing unique features of the Xtensa LX processor which allow direct high-speed data communication between the processors and thereby avoid the time delays of bus-based data traffic, Epson’s engineers were able to reduce the time required to print a single page to less than a third of that required by previous generation inkjet printers. These new printers can print borderless 4 x 6 photos as fast as the highest printing speed for black and white text.

For more information on this interesting application, see

Sony Licenses Xtensa LX2

Sony Corporation has renewed and updated its license for Tensilica’s Xtensa LX2 configurable processor.

“Sony’s engineers realize the value of using a configurable processor to lower power and significantly improve performance in hand-held, battery powered devices,” stated Chris Rowen, Tensilica’s president and CEO. “We expect the Xtensa LX2 processor core will be used in designing Sony’s future consumer product and look forward to working with them on their next-generation design projects.”

Tuesday, January 23, 2007

CoWare’s Platform Architect Fully Supports Tensilica’s Configurable and Standard Processors

CoWare and Tensilica announced they have collaborated to deliver a comprehensive ESL design environment with CoWare’s Platform Architect for Tensilica’s processors. CoWare will distribute a SystemC-based Processor Support Package (PSP) with the flexibility to match all configurations of Tensilica’s Xtensa configurable processor family as well as Tensilica’s Diamond Standard family of processor cores.

Design engineers can now use CoWare’s Platform Architect ESL environment to do full architectural exploration, design verification, and software development when designing with Tensilica’s Diamond Standard processors and Tensilica’s highly-configurable Xtensa processors. This collaboration provides a huge productivity boost for SoC designers, as it not only speeds the design process, but also enables parallel development of the hardware and software.

For more information, see

Monday, January 22, 2007

Tensilica Introduces TurboXim Fast Functional Simulator 40-80x Faster than ISS, Automatic SystemC Model Generation

Tensilica announced the new TurboXim fast functional simulator, which is 40 to 80 times faster than Tensilica’s proven cycle-accurate ISS (Instruction Set Simulator).

Tensilica also introduced its ability to automatically generate SystemC models to match all possible configurations of its Xtensa configurable processors and Diamond Standard series processors.

These introductions significantly speed ESL (embedded system level) design and architectural exploration for SOC (system-on-chip) design using one or more Xtensa configurable processors or Diamond Standard processors.

For more information, see

Friday, January 19, 2007

CPU Cores and IP for Networking Seminar

On January 31, The Linley Group will host the first seminar of its Linley Tech 2007 series. This one-day event will focus on CPU cores and other licensable intellectual property (IP) and is intended for designers of ASICs and SoCs (systems on a chip). Leading IP vendors will explain how their technology can be used in networking and communications applications. Get the information you need to jumpstart your design!

The seminar will open with a presentation from The Linley Group highlighting recent trends in intellectual property. The program includes a session on CPU cores for ASICs and SOCs, featuring presentations on how to get the most out of popular ARM, MIPS, Power, and Tensilica CPUs. The event also includes a session on other IP for networking, including security, high-speed interfaces, and wireless technology. We have an outstanding lineup of speakers and talks, including:

Sumit Gupta, a product marketing manager at Tensilica, will present "Networking Applications for Xtensa Configurable CPU Cores."

This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Register now to guarantee your place. The seminar is targeted at ASIC and SoC designers, OEMs, press, and the financial community. Your free attendance is made possible by our event sponsors: Freescale, Tensilica, SafeNet, MIPS, Rambus, IBM, and ARM. Sign up now at:

Tuesday, January 16, 2007

Virage Logic - Tensilica Net Seminar

Optimize Area, Performance or Power with Tensilica and Virage Logic Core-Optimized IP Kits
January 24, 2007 - 11 am PST/2 pm EST - Register Now!

Join Virage Logic and Tensilica for an informative technical webinar on the recently introduced Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family. Specifically tuned to optimize the performance of Tensilica's Diamond Standard product line processor cores, this joint collaboration provides mutual customers with physical IP that leverages Virage Logic's silicon proven embedded memory IP and standard cell libraries to meet a variety of market requirements. The Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores on TSMC’s 130-nanometer (nm) and 90nm G processes.

Learn how customers can utilize easy instant access to a series of jointly-developed Core-Optimized IP Kits specifically optimized for each of the Diamond cores that allows designers to target area, performance or power for a greater competitive advantage.

You won't want to miss this exclusive technical webinar where Virage Logic and Tensilica will jointly provide an overview of the Core-Optimized IP Kits and then show how Virage Logic's highly differentiated, silicon proven semiconductor IP has been optimized specifically to enhance Tensilica’s Diamond Standard processor cores.

Thursday, January 11, 2007

Tensilica’s Diamond Standard Processors Receive Prestigious Portable Design Editor's Choice Award

Portable Design Magazine named Tensilica's Diamond Standard Processor family as a recipient of its prestigious Editor's Choice Award for 2006. Only 11 products were picked for this award for 2006.

According to Portable Design, “Every year Portable Design reviews several hundred products intended to make life easier for designers of portable electronic devices... We recognize the best of the best with our 2006 Editor's Choice Award. We believe that these products are indicative of the creativity our readers bring to bear, and they're worthy of the wider recognition that this award will bring."

See Portable Design's Editor's Choice award recipients.

Thursday, January 04, 2007

Tensilica Mourns Friend and Board Member, Richard Newton

Tensilica mourns the death of our friend and board member Richard Newton. Rich's energetic presence will be missed by us all. We extend our sympathies to his family and friends. (EETimes story on his passing)