Tuesday, September 14, 2010
"We selected Tensilica's DPUs because of their remarkable ability to be customized with high-bandwidth, efficient interfaces, such as FIFO-like queues, to quickly stream data into and out of the processor," stated Sean Campeau, AppliedMicro's senior manager of engineering. "These high-speed connections bypass the main system bus altogether, allowing us to implement functions in the processor that previously could only meet our performance targets by being implemented in RTL (register transfer level) logic. Implementing these functions in a processor speeds our design effort considerably and gives us a much more flexible solution."
Posted by Tensilica at 10:15 AM