Why Not Use Processors in the SOC Dataplane?

Tensilica offers the core technology that overcomes the top four objections to using processors in the dataplane:
1. Data throughput - Tensilica allows designers to bypass the main system bus, just like a block of RTL.
2. Fit into hardware design flow - We provide glueless pin-level co-simulation of the ISS with Verilog simulators from the leading EDA companies.
3. Processing speed - Customization yields speeds 10 to 100 times that of traditional processors and DSPs.
4. Customization challenges - Our process is automated - you can't break our cores!