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Tuesday, November 29, 2005

E L & Associates Becomes Tensilica Authorized Design Center

E L & Associates, of Pleasanton, Calif., is now an authorized Tensilica design center. E L & Associates already supports several Tensilica customers with their system-on-chip (SOC) design programs, and is a leader in the design (RTL to GDS2), design-for-test (DFT), and design-for-manufacturing (DFM) integrated solutions for complex SOC architectures. For more information, see http://www.tensilica.com/partners/soc_el.htm

Monday, November 14, 2005

New Office in Seoul, Korea

Tensilica hired Myeong-heum Yeon as managing and sales director of our Korean office. Mr. Yeon has a strong background at major companies including Texas Instruments, Samsung and LG Electronics. Tensilica has major customers in Korea, including LG Electronics, which has designed Tensilica’s Xtensa processor into the LG-LT1000 and LG-KT1000 DMB phones.

“Primarily due to the design flexibility, performance and low power that Tensilica technology offers, Korean consumer and communications manufacturers have been very receptive to our Xtensa configurable processor family,” stated Antonio J. Viana, Tensilica’s senior vice president of sales. “Now that Myeong-heum has joined our company, we have set up a formal Korean presence to further support this important region. Myeong-heum will soon be adding further staff.”

Tensilica’s new office is at 27th FL., Korea World Trade Center 159-1 Samsung-dong, Kangnam-gu, Seoul 135-729, Korea, tel: 82-2-6007-2745 fax: 82-2-6007-2746. Mr. Yeon can be reached via email at mhyeon@tensilica.com.

Tuesday, November 08, 2005

“Top Product of EDN China 2005 Innovation Award”

Tensilica's Xtensa LX processor and Vectra LX DSP Engine have been honored with the “Top Product of EDN China 2005 Innovation Award” by EDN China magazine.

“Tensilica revolutionizes the traditional SOC design methodology. Designers can use Tensilica’s configurable processors as an alternative to the RTL hardware logic part in traditional SOC development, so as to reduce the total investment in SOC design and the time for SOC verification,” remarked John Mu, Executive Editor-in-Chief of EDN China. “Tensilica’s configurable processor and development tools offer a totally new solution and choice for engineers in SOC design.”

Tuesday, October 25, 2005

Fall Processor Forum Presentation

Tensilica's Fall Processor Forum presentation is now posted on our web site. Sure, it's not the same as actually being there, but you can see " High-Performance Multicore Video DecoderTechnology Preview" at http://www.tensilica.com/pdf/FPF_05.pdf.

Monday, October 24, 2005

New Ultra-low-power Xtensa 6 Processor

Tensilica's new Xtensa 6 configurable and extensible processor core for system-on-chip (SOC) design replaces Tensilica's workhorse Xtensa V processor. Xtensa 6 adds three major enhancements: the ability to automatically customize it from a C/C++ based algorithm using Tensilica's proven XPRES Compiler; approximately 30 percent lower power than Xtensa V; and advanced security provisions in MMU-enabled configurations through a "no execute" bit that provides enhanced protection against malicious code.

"Xtensa 6 provides SOC designers with the fastest, most cost-effective SOC block design tool in the industry," stated Steve Roddy, vice president of marketing, Tensilica. "By using our popular XPRES Compiler, in less than an hour designers can create application-specific building blocks that can serve as either conventional control processors or as a suitable alternative to RTL-based hardware block design, but in a fraction of the time and without the verification headaches. We expect this product to significantly widen our customer base because it fully automates time-and-resource intensive IC design steps and adds programmability to the post-silicon design, a crucial value-add enabler in fast-moving, high-volume SOC markets."

Read more at http://www.tensilica.com/news_events/pr_2005_10_24.htm and see the Products section of our web site.

Thursday, October 06, 2005

New Xtensa HiFi 2 Audio Engine Announced

Tensilica, Inc., today announced the Xtensa HiFi 2 Audio Engine, an add-on package for Tensilica’s proven Xtensa LX processor, optimized specifically for today’s consumer audio functions. Tensilica also announced a comprehensive set of software encoders and decoders for all popular audio standards, including Dolby Digital AC-3, microQ from QSound Labs, MP3, MPEG-2/4 AAC LC and aacPlusTM, WMA (Windows Media Audio), and AMR (Adaptive Multi-Rate speech). As a low-power turnkey solution, the Xtensa HiFi 2 Audio Engine enables system-on-chip (SOC) designers to quickly design audio-enabled devices such as cellular phones, portable music players, DVD drives, and set-top boxes.

“By the end of 2005, our customers will have shipped tens of millions of units that include our first-generation Xtensa HiFi Audio Engine,” said Chris Rowen, president and CEO of Tensilica. “This new generation product supports additional audio standards and is based on our leading-edge Xtensa LX processor, so it’s faster, lower power, smaller and more flexible.”

See http://www.tensilica.com/news_events/pr_2005_10_06.htm for more information

QSound Labs' microQ Technology Licensed

QSound’s microQ audio components have been ported to run on Tensilica’s new Xtensa HiFi2 Audio Engine. microQ is a compact, hardware-independent and highly efficient software audio engine providing functions such as polyphonic ringtones, video game sounds, music playback, digital effects and recording for portable applications, including Internet appliances, hand-held and mobile devices. For more information, see http://www.tensilica.com/news_events/pr_2005_10_06a.htm .

QSound Labs' microQ Technology Licensed

QSound’s microQ audio components have been ported to run on Tensilica’s new Xtensa HiFi2 Audio Engine. microQ is a compact, hardware-independent and highly efficient software audio engine providing functions such as polyphonic ringtones, video game sounds, music playback, digital effects and recording for portable applications, including Internet appliances, hand-held and mobile devices. For more information, see http://www.tensilica.com/news_events/pr_2005_10_06a.htm .

Coding Technologies' aacPlus Licensed

Tensilica has selected Coding Technologies’ aacPlus codec for its Xtensa HiFi 2 Audio Engine. Coding Technologies’ is a recognized innovator in digital audio technology and their well executed aacPlus implementation greatly simplified the development of a highly optimized port for our Xtensa HiFi 2 Audio Engine. For more information, read http://www.tensilica.com/news_events/pr_2005_10_06b.htm

Monday, September 26, 2005

Do You Believe Tensilica's Marketing Claims?

This question was posed on John Cooley's Deepchip web site (see http://www.deepchip.com/items/0447-06.html). A reader posted, "TenSilica is closer to ARC than ARM, but when I last looked, TenSilica was miles ahead of ARC. ARC give you more flexibility in that you writethe entire extension in Verilog, and you are allowed to do pretty muchwhatever you want, while TenSilica is more constraining, but TenSilica'sstuff is far more polished, with everything being automated. I was very impressed with what I saw from TenSilica, and I wouldn'thesitate to recommend them. In my experience, it's rare to find a companywhose products actually live up to the marketing claims, especially in IP. " Read the full story.

Atheros Licenses Xtensa Processor

Atheros, a leading provider of wireless solutions, has licensed the Xtensa processor for use in future designs. "We selected Tensilica's Xtensa processor because of its high-performance, low power and small size which are ideal for a wide range of very compact wireless applications," said Rick Bahr, VP of Engineering for Atheros Communications. "Xtensa's configurable and extensible microprocessor core provides Atheros and our customers with a high level of design flexibility required to satisfy the growing array of end-product application requirements."

See the press release at http://www.tensilica.com/news_events/pr_2005_09_26.htm

Thursday, September 22, 2005

Congratulation Ikanos

Congratulations to Ikanos Communications on their successful initial public offering. [NASDAQ symbol: IKAN]. Tensilica is proud to be a key ingredient in their success. Ikanos uses the Xtensa processor as the heart of its Burst Mode Engine (BME) chip, which is in the SmartLeap 8100, SmartLeap 8800 and CleverConnect 150 chip sets.

Tuesday, September 20, 2005

Chris Rowen to Keynote EMSOFT Conference

Tensilica's president and CEO, Chris Rowen, will be the keynote speaker at tomorrow's EMSOFT conference. His speech will discuss "Multiprocessor SOC Design: Revolution Now!" Already, Tensilica's customers use, on average, 6 processors per SOC design, so the multiple processor revolution certainly is occuring. One customer used almost 200 processors in a recent networking design.

EMSOFT is the leading conference for research in embedded systems software. Embedded computing pervades everyday life. Embedded software must meet demanding criteria for correctness, performance, power consumption, and development cost. EMSOFT is the flagship conference of the ACM Special Interest Group on Embedded Computing (SIGBED).

Chris' talk is at 8:30 am on Wednesday, September 21, in Jersey City, New Jersey. See http://www.princeton.edu/%7Ewolf/EMSOFT-2005/index.htm for more information on this conference.

Monday, August 29, 2005

90nm announcements today

Today Tensilica issued three press releases that show that our Xtensa processors are proven in 90nm technology. See the front page of our new web site, www.tensilica.com, to read the text of these announcements. You'll find that our Xtensa LX processor reached the highest clock rate of any licensable 32-bit processor on the market in 90 nm technology. We have statistics from STMicroelectronic's runs and TSMC simulations. We also have details on the EDA flow used, with tools from Cadence and Synopsys.

Why is this so important? It means that our base architecture, without any modifications, is superior to other 32-bit architectures. The Xtensa processor is ideal for applications ranging from a simple control processor to applications where performance is critical.

Thursday, August 25, 2005

New Web Site

Yes, we've been kind of qiet with our blog this summer. But we didn't take the summer off. We're getting ready to launch our new web site. We're adding two important new sections: Methodology and Markets. Lots of new, good content. A more sophisticated look and feel. And it's been a lot of work. We're in final testing now, and we plan to go "live" this weekend. Check it out at www.tensilica.com.

Wednesday, June 08, 2005

See Tensilica at DAC

You won't be able to miss Tensilica if you're going to DAC next week in Anaheim, CA. We caught baseball fever from playing the Konami baseball game (Xtensa processor diving the video inside) and you can try, too! Enter our raffle for 2 world series tickets! Other features include:

Tuesday, June 14 11:30 AM- 12:15 PM, Booth 2269 PAVILION PANELESL: Is it Just MATLAB® and Excel Spreadsheets? Grant Martin - moderator

Wednesday, June 15 2:00-5:00 PM Hands-on Tutorial: Using Configurable Processors to Replace RTL Blocks Register Now!

Thursday, June 16 Session 43, Room 210AB 10:30 AM - 12:00 PM Implementing Low-Power Configurable Processors - Practical Options and TradeoffsAshish Dixit - presenter

Thursday, June 16Session 47, Room 210CD 12:15 - 1:45 PM Smart Diagnostics for Configurable Processor Verification Sadik Ezer, presenter

Thursday, June 16 Session 52, Room 210CD 4:30 - 6:00 PM - Panel: Platform ASIC Apprentices: Who Will Survive Your Boardroom? Steve Leibson, presenter

Friday, June 17 Friday Tutorial, Room 207ABC 9:00 AM - 5:00 PM #6 - Design of SoC with Embedded Processors Chris Rowen - CEO, speaker

Tuesday, June 07, 2005

Antonio J. Viana - New Sr. VP of Sales

Antonio J. Viana has joined Tensilica as senior vice president of worldwide sales. Viana joined Tensilica from ARM, Ltd., where he was vice president of North American sales.

“Tensilica has intelligently automated the customization of processors to achieve RTL-equivalent performance and much lower power dissipation,” stated Viana. “Considering all of the challenges of SOC design, time-to-market is typically one of the most significant. Tensilica’s technology is best poised to help customers meet the current and future challenges of SOC design, in particular, time-to-market. I am very excited to be a part of the Tensilica family.”

Friday, May 20, 2005

Agilent Licenses Xtensa for Image Processing

Agilent Technologies, Inc.’s Imaging Systems Division has signed a broad technology-access agreement to license Tensilica’s Xtensa V and Xtensa LX configurable processor technologies for next-generation products. This follows the successful deployment of Xtensa V processors by Agilent in several recently introduced imaging products.
For more information, see http://www.tensilica.com/html/pr_2005_05_19.html.

Tuesday, May 17, 2005

ARM's BDTI Benchmark Scores

On May 16 ARM announced “Class-leading” BDTi benchmark scores (see http://www.arm.com/news/9103.html). However, ARM’s “class” only included their processor and the MIPS 24Kc processor.

There were several other processors that ARM decided not to mention, including Tensilica’s Xtensa LX processor, which achieved a 5x higher score than the ARM11 processor. Other processors not mentioned but also surpassing ARM’s results include the CEVA-X1620, LSI Logic’s ZSP500, StarCore SC1200, and StarCore SC1400. For full BDTI results, see http://www.bdti.com/bdtimark/core_scores.pdf.

Monday, May 16, 2005

Xtensa LX Processor Tops EEMBC Networking 2.0 Benchmarks

Tensilica's Xtensa LX processor achieved the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBCĂ’). Xtensa LX is the first licensable processor core to complete certification on this challenging benchmark suite.

EEMBC benchmark scores, based on simulation, show that an optimized Xtensa LX processor core is significantly faster on a per-MHz basis than the only two other processors certified to date, the 1GHz PowerPC 750GX and 1.4 GHz PowerPC MPC7447A, both of which are full-chip, standard product processors. The Xtensa LX processor delivers this outstanding performance while simultaneously delivering a 4X code density advantage and more than a 100X advantage in both die area and power dissipation.

For all the details on this important benchmark, see http://www.tensilica.com/html/pr_2005_05_16.html.

Thursday, May 12, 2005

Tensilica Preview at Spring Processor Forum

Next Wednesday, May 18, Tensilica will preview our next-generation audio engine at the Spring Processor Forum in San Jose (see http://www.in-stat.com/spf/05/conf.htm ). We'll have this product ready for a formal announcement in the fall, but if you want a sneak preview, stop by and hear what we have to say. By using a configurable processor, we're able to really optimize the design for high-speed audio streams.

Wednesday, May 11, 2005

Tensilica and EVE Speed SoC Development Times

Tensilica is working with Emulation and Verification Engineering (EVE) to speed the design of complex SoCs with multiple Xtensa processors. Tensilica’s customers will be able to download pre-verified RTL code produced by Tensilica’s Xtensa Processor Generator into EVE’s hardware prototyping platform for integrated whole-chip design verification. Tensilica’s Xtensa Xplorer development environment will be linked to EVE’s ZeBu hardware-based verification product to provide hardware/software co-verification and improve overall SoC simulation and debugging. By providing our users with easy access to EVE’s ZeBu prototyping platform, they should be able to quickly verify their entire SOC designs.

Friday, May 06, 2005

Great Article by Jack Ganssle

Jack Ganssle, the guru for many software developers, wrote a great piece for Embedded Systems Programming and you can see it at http://www.embedded.com/showArticle.jhtml?articleID=161600589. He shows that the best way to cut software costs is to divide and conquer. By dividing projects into smaller, more manageable tasks that each run on its own processor, overall software costs can be cut significantly. Tensilica's customers have been doing this for years. By employing multiple configurable processors, each tailored to the exact task at hand, these customers are cutting design time and software development time.

Friday, April 22, 2005

sci-worx to use Xtensa for Video Cores

sci-worx will be designing several system-on-chip (SOC) intellectual property (IP) blocks, including H.264, WMV-9 and MPEG-2 for High-Definition TV, with multiple Tensilica Xtensa LX configurable processors.
Current generation IP solutions from sci-worx were designed with Register Transfer Level (RTL) logic methodologies. By adding a configurable processor-based design approach to its portfolio, sci-worx will speed design time and enjoy more flexibility to offer easier upgradability through software.

In addition to designing with Tensilica’s Xtensa configurable processors, sci-worx will become Tensilica’s first value added reseller (VAR), distributing Tensilica processors as part of larger sci-worx IP subsystems. sci-worx customers will be able to sign one license agreement with sci-worx that includes the necessary provisions for licensing the Xtensa processors inside sci-worx designed IP blocks.

“The market requirement for multi-standard video codecs for SD and HD resolutions requires more flexible solutions to address the high volume consumer market,” stated Young-Hun Kluge, vice president of sales and marketing, sci-worx, “We’ll be able to get new IP out substantially faster and provide greater flexibility to our customers by using Xtensa processors instead of traditional RTL design methods.”

“sci-worx is an excellent example of a company that understands the benefits of using processors instead of hard coding algorithms into logic gates,” stated Steve Roddy, Tensilica’s vice president of marketing. “We look forward to working as a partner with sci-worx as they complete their new IP designs.”

For more information, see http://www.tensilica.com/html/pr_2005_04_20.html

Wednesday, April 06, 2005

VDSL-2 Data-Path Design Partnership with UpZide

UpZide is developing a reference design utilizing multiple Xtensa LX processors to implement the VDSL2 (second generation Very high-speed Digital Subscriber Line) standard. Because the standard is evolving, it’s essential that the VDSL2 data-path component be designed with the flexibility required to adapt to all possible changes. By designing with highly configurable Xtensa processors rather than RTL, and by extending the instruction set to handle the data-intensive demands of the VDSL2 standard, UpZide will be able to make available for license a fast, efficient, and programmable solution for this rapidly growing market.

The VDSL2 standard provides broadband connections at speeds of up to 100 Mbps symmetrical, which is fast enough to deliver the “triple play” applications of voice, data and video to a wide audience. This technology is seen as key to delivering VoIP (voice over Internet protocol), VoD (video on demand) and HDTV (high-definition television) simultaneously over standard telephone lines. For more information, see http://www.tensilica.com/html/pr_2005_04_05.html

Tuesday, March 29, 2005

FS2 Debugger Now Available

The FS2 System Navigator is available now for debug and system integration of system-on-chip (SOC) designs with Tensilica Xtensa V and Xtensa LX configurable and extensible processors. The FS2 System Navigator tool supports designs that employ multiple Xtensa processors – a hallmark of the Tensilica architecture. The FS2 System Navigator architecture offers optional interfaces for FS2 Bus Navigator tools, which provide tracing and bus level analysis of OCP, AMBA, or custom bus interfaces. For more information, see http://www.tensilica.com/html/pr_2005_03_29.html .

Monday, March 28, 2005

Tensilica Tops EEMBC OA Benchmark

The Xtensa LX configurable processor posted the highest score ever recorded for a licensable processor core, and the highest absolute score ever published for any processor, on the Office Automation benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC). The EEMBC benchmark scores, independently certified by the EEMBC Certification Laboratories (ECL), confirm that the Xtensa LX processor is nearly four times faster than the much larger PowerPC 440GX core, and more than 4 times as powerful as the 64-bit MIPS 20Kc processor.

The certified EEMBC OAmark scores are:
· 4.19523 – Optimized Xtensa LX processor
· 1.07999 – Out-of-the-box PowerPC 440GX processor
· 0.98880 – Out-of-the-box Xtensa LX processor
· 0.89033 – Out-of-the-box MIPS 20Kc processor
. 0.75975 – Out of the box ARM 1026EJ-S processor

For more detail, see http://www.tensilica.com/html/pr_2005_03_28.html .

Wednesday, March 23, 2005

Book by Chris Rowen

“Engineering the Complex SOC,” by Chris Rowen, CEO of Tensilica, and editor Steve Leibson, Tensilica’s Technology Evangelist, describes an emerging SOC design methodology that uses configurable, extensible processors as basic building blocks. This allows chip designers to finish larger projects in much less time, with higher quality results. The book uses real-world illustrations extensively, both in the form of case studies about architecture decisions and in short examples that communicate the flavor and the power of these methods. Find out more about this powerful book at http://www.tensilica.com/html/book.html .

Monday, March 21, 2005

MPR Names Xtensa LX the “Best IP-Core Processor” of 2004

The Xtensa LX processor has won the 2004 Microprocessor Report (MPR) Analysts’ Choice Award for Best Intellectual-Property (IP) Core. MPR selected the Xtensa LX core for its market-leading performance (verified by independent benchmark results), low power consumption, unmatched architectural flexibility, powerful Vectra LX DSP engine and unique XPRES (Xtensa PRocessor Extension Synthesis) design tools.

“We saw significant activity in the IP-core market this year with many companies announcing new products, but Tensilica’s introduction of the Xtensa LX and its revolutionary tool, the XPRES design compiler, made it the clear winner,” said Tom R. Halfhill, Senior Analyst, Microprocessor Report. “Even without XPRES, Xtensa LX would be the leading contender for this award, but the combination is unbeatable.”

Read the article from MPR at http://www.tensilica.com/Best_Processor_Core_2004.pdf

Wednesday, March 16, 2005

Great Synopsys Users Group (SNUG) Event

Last night, Tensilica had a booth at the annual Synopsys Users Group vendor fair at the Santa Clara Marriott. As usual, Synopsys had lots of great food and drinks. The ballroom was full of booths from various companies that fit into and around the Synopsys design flow. We heard that this was the most attended SNUG yet, with over 1,000 registered attendees. The room certainly was packed, and lots of people stopped by to see us. We had a demonstration of our XPRES tool, which takes a standard C/C++ algorithm and automatically configures an Xtensa LX processor to run that algorithm at RTL-equivalent speeds.

Monday, March 14, 2005

NEC Electronics America Distributes Xtensa

“The Xtensa processors are a welcome addition to NEC Electronics America’s ASIC IP library. Their customization capabilities make them ideal replacements for blocks of logic that previously would be handcrafted in Verilog or VHDL. By using processors instead of logic blocks, our customers will benefit from the inherent programmability, reduced verification time and much faster design times,” said Phillip LoPresti, associate vice president and general manager, custom LSI strategic business unit, NEC Electronics America. For more information, see http://www.tensilica.com/html/pr_2005_03_14.html

Sunday, March 13, 2005

New White Papers on FLIX and XPRES

Find out more about two of Tensilica’s most exciting technologies:

http://www.tensilica.com/FLIX_White_Paper_v2.pdf - FLIX: Fast Relief for Performance Hungry Embedded Applications

http://www.tensilica.com/XPRES-Triple-Threat_Solution.pdf - XPRES Compiler: Triple-Threat Solution to Code Performance Challenges

Thursday, March 10, 2005

Tensilica Expands into China

“We are pleased to establish a direct presence in China where we can work closely with the systems and semiconductor companies to help them differentiate and innovate using our automated design approach,” said Chris Rowen, president and CEO of Tensilica. More information: http://www.tensilica.com/html/pr_2005_03_10.html

Tuesday, March 08, 2005

FS2 Offers Multi-Core Debugging

The FS2 System Navigator tool supports designs that employ multiple Xtensa processors – a hallmark of the Tensilica architecture. The FS2 System Navigator architecture offers optional interfaces for FS2 Bus Navigator tools, which provide tracing and bus level analysis of OCP, AMBA, or custom bus interfaces. See http://www.tensilica.com/html/pr_2005_03_08.html

Monday, March 07, 2005

New VP of Customer Engineering

Dan Weed is New VP, Customer Engineering

Dan will be responsible for organizing and managing Tensilica’s technical support and customer engineering operations. He has more than 25 years experience in design center management, marketing and engineering at Cadence Design Systems, LSI Logic, Fujitsu Microelectronics and Texas Instruments. See http://www.tensilica.com/html/pr_2005_03_07a.html