Thursday, December 20, 2007
For more information, see http://www.tensilica.com/news_events/pr_2007_12_18.htm
Thursday, December 13, 2007
These new capabilities provide designers with the most productive configurable processor design environment, with automated features that ensure each processor design is correct by construction. For more information, see http://www.tensilica.com/news_events/pr_2007_12_10_xtensa.htm
For more information, see http://www.tensilica.com/news_events/pr_2007_12_10_trax.htm
Wednesday, December 05, 2007
NEC Electronics America Offers Free License for Tensilica's Diamond Standard 106Micro Processor Core
To join the webcast, go to:https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=97638&sessionid=1&key=F68674417431BD07F49139A0A29B605B&partnerref =evite1&sourcepage=register. For those unable to attend the livewebcast, it will be available on demand for one year.
Monday, December 03, 2007
ThreadX is Express Logic’s small, fast, royalty-free RTOS for demanding real-time applications. Its royalty-free business model makes ThreadX extremely attractive for high-volume devices. ThreadX’s ease-of-use enables ThreadX-powered devices to get to market on time and within budget, which accounts for ThreadX’s success in the marketplace and its high-volume implementations. ThreadX has been widely embraced and is currently deployed in excess of 450 million electronic products. ThreadX is complemented by Express Logic’s NetX TCP/IP stack, FileX file system, USBX USB stack, and PEGX GUI development kit, all of which also are available for Tensilica’s new Diamond Standard 106Micro.
For more information, see http://www.tensilica.com/news_events/pr_2007_12_3.htm
Friday, November 30, 2007
“We needed a supplier we could depend on, and we were very impressed with Tensilica’s support for their products,” stated Mayte Bacete, operations director, DS2. “The Xtensa configurable processor gives us the right mix of performance and low power that we need for these chip designs.”
See the full press release at http://www.tensilica.com/news_events/pr_2007_11_28.htm
Monday, November 26, 2007
For more information, see http://www.tensilica.com/news_events/pr_2007_11_26.htm
Tuesday, November 20, 2007
By integrating Tensilica’s Diamond Standard 106Micro, the smallest licensable 32-bit processor core, with CoWare Platform Architect, designers get the first and most productive ESL 2.0 solution for platform architecture design, platform verification, and software development using Tensilica’s processor cores.
For more information: http://www.tensilica.com/news_events/pr_2007_11_20.htm
“By working with Tensilica, we can help our customers incorporate our advanced sound technologies very quickly and easily,” stated Brian Towne, Senior Vice President and General Manager, Consumer Division at DTS. “The market for high definition audio systems is beginning to materialize and the availability of DTS technologies on the HiFi 2 audio engine will help enable the accelerating growth.”
For more information: http://www.tensilica.com/news_events/pr_2007_11_13.htm
Monday, November 12, 2007
The low-power Diamond Standard 106Micro is designed for simple controller applications in SOC (system-on-chip) designs, and an ideal choice for designers migrating from 8-bit and 16-bit microcontrollers to 32-bit processors. All Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners, who provide support with operating systems, design services, hardware prototyping and emulation, libraries and memories, EDA tools, and peripherals. For more information, see http://www.tensilica.com/news_events/pr_2007_11_05_106.htm
Friday, November 02, 2007
Valens Semiconductor Picks Diamond Standard 108Mini for chip that Ensures High-Quality Home Audio-Video Networking
For more information, see http://www.tensilica.com/news_events/pr_2007_10_31.htm
Monday, October 15, 2007
“One of our main target application areas is battery operated mobile/portable devices where power consumption is a very critical factor.” stated Mohammad Moradi, Co-Founder and Executive VP of Engineering at MediaPhy. “As such, we have chosen the Tensilica Diamond Standard 108Mini processor core to benefit from its low power consumption and small area at the same time.”
Tuesday, September 18, 2007
ZeBu (for Zero Bugs) gives Tensilica verification engineers an easy-to-use and affordable solution that combines the best aspects of traditional emulation and rapid prototyping systems. It is used in Tensilica’s system-level regression testing, hardware/software integration, application and codec development, conformance testing and profiling. ZeBu also proved useful in validating multi-processor synchronous debugging. In addition to allowing software engineers to validate codecs, ZeBu also helped Tensilica’s engineers find subtle bugs during product development related to clock tree issues missed during register transfer level (RTL) simulation.
For more information, see http://www.tensilica.com/news_events/pr_2007_09_18.htm
Monday, September 17, 2007
ChipEstimate.com was launched in 2005 to provide comprehensive chip planning capabilities to the electronics and semiconductor community. In addition to the comprehensive IP catalog, designers can use the InCyte software available through the website to plan their next chips and explore die size, power, leakage and cost tradeoffs. Tensilica IP can now be searched for and considered in chip estimations though the portal.
A complete list of Chip Estimate IP partners can be seen at http://www.chipestimate.com/vendorlist.php.
Monday, September 10, 2007
“The HiFi 2 Audio Engine is a very well optimized core for all audio functions, ranging from low-power MP3 to high-end surround sound,” stated Michael Vulikh, CEO of P-Product. “The audio centric instructions Tensilica created enable easy programming in C code, avoiding the time consuming assembly-level programming usually required when porting audio algorithms to the typical DSPs and CPUs. The HiFi2 audio engine allows us to deliver superior MHz performance with far less development effort.”
P-Product has already ported audio software to Tensilica's HiFi 2 Audio Engine and has significant expertise in audio and video software porting.
Application Processors and Controllers,” highlighting the way for SOC (system on chip) designers to achieve high performance while keeping the processor core area very small. The seminar will show the process of evaluating code for hot spots and then accelerlerating those functions using configuration options and the Verilog-like Tensilica Instruction Extension (TIE) language.
This webcast is Wednesday, September 12, at 11:00 a.m. PT / 2 p.m. ET. Sign up here: https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=92084&sessionid=1&key=477F1AD28B50C3D5E0FA6677040660D1&partnerref=sponlink&sourcepage=register
Wednesday, September 05, 2007
Tallika’s security solution includes a 32-bit AHB/APB backbone and Tallika’s linked-list-based DMA controller integrated with its security IP blocks - AES/TDES/SHA/MD5 on the AHB bus and 2048-bit native exponentiation engine on the APB bus. The Secure FPGA Platform is based on Xilinx Virtex4 LX160 FPGA devices and comes with a complete software library to access security functions as well as with a full implementation of RSA encrypt, decrypt, and key-pair generation (including acceleration for Primality testing). The solution is also available for license by Tallika as soft IP for ASIC development.
The Secure Platform core IP and FPGA platform are available now from Tallika. More information regarding this solution can be found at http://www.tallika.com/products_security_secure_soc.htm.
Monday, August 27, 2007
and Lenovo in their latest notebook PC products. Dell’s Inspiron 1720 notebook and Lenovo’s ThinkPad T61/T61p 15.4-inch widescreen notebook are part of the very first wave of Wireless USB platform certifications awarded by the USB Implementers Forum that contain WiQuest's chips, which contain Xtensa processors.
Monday, August 20, 2007
* Fast OFDM on Xtensa Processors
* Implementing A Mutex and Barrier Synchronization Library on Xtensa
* Optimizing for Energy using the Xenergy Energy Optimizator Tool
SiBEAM, Inc. Selects Tensilica Configurable Processor for Baseband DSP in Wireless Link for HDTV Devices
“SiBEAM has developed its wireless communications products to deliver high quality wireless video solutions for consumer electronics and display applications. These applications demand high data rate transmission to multiple devices within an indoor wireless environment using conventional CMOS silicon,” said Kumar Mahesh, manager of MAC and Software Design for SiBEAM, Inc. “We selected Tensilica’s Xtensa processor for its ability to help us achieve our goal of developing innovative-multi-gigabit, lower-power mmWave communications products. By optimizing the Xtensa processor into a tailored processor core, this enables our products to attain the performance these wireless applications demand.”
For more information, see http://www.tensilica.com/news_events/pr_2007_08_20.htm
Friday, August 10, 2007
“Low-Power, Low-Overhead, High-Fidelity Digital Sound for SOCs”
Live Webcast Wednesday, August 15, at 11:00 a.m. PT
Tensilica will present a live webcast, discussing how most consumer products must support multiple codecs and offer a broad range of audio-enhancement features. All of these factors have resulted in a high demand for a flexible, high-performance, low-power audio engine that adds digital-sound capabilities to an SOC with the least amount of design effort and a small on-chip footprint. This online seminar presents a proven way to add low-power, low-overhead, high-fidelity audio to SOC designs.
The presenter for the August 15th broadcast will be Steve Leibson, Technology Evangelist, Tensilica. Leibson, the author of several books on integrated circuit design, spent 15 years as an award-winning technology journalist, serving as Editor in Chief of EDN, the Microprocessor Report, and Embedded Developers Journal. He also served as an engineer at several companies, including HP.
To sign up for this event, visit http://tensilica.com/news_events/events.htm
Friday, August 03, 2007
“Tensilica’s Diamond Standard 38xVDO Video Engine family is the most capable processor core-based video solution on the market today, supplying full D1 resolution Main Profile H.264 performance,” stated Madhukar Dev, CEO, Tata Elxsi. “And the HiFi 2 Audio Engine is proven in designs that are shipping in huge volumes right now. Our turnkey SOC design capability and proven strengths in multimedia design will help Tensilica’s customers quickly integrate these powerful engines into their SOC designs, reducing product development time and costs. Our network of offices and strong presence in key geographies such as US and Europe and Asia, including Japan, Taiwan and South Korea, provides customers with easy access to world-class multimedia system and engineering expertise.”
Tuesday, July 17, 2007
Wednesday, July 18 - Reduce Power and Energy Consumption in Low-Power SOCs Through ISA Extension - 11 am pacific, 2 pm EST - Sign up at https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=56190&sessionid=1&key=09644E927D284A86219B1D1336A920
Thursday, July 19 - Low Cost and Low Risk 32-bit Controllers for Designing AMBA-based SOCs - 10 am pacific, 1 pm EST - Sign up at
Wednesday, June 20, 2007
With the RTL Compiler multi-objective optimization, customers can achieve significant advantages in area, speed and performance. In tests, Tensilica achieved a 10 percent increase in speed and a reduction of cell area of 5 percent. The RTL Compiler global synthesis solution improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.
For more information: http://www.tensilica.com/news_events/pr_2007_06_19_cadence.htm
Tuesday, June 19, 2007
Aftek has considerable expertise in IP (intellectual property) integration as well as the development of system and chip specifications, hardware-software partitioning, development of reference models, and analysis of performance trade-offs. They have successful tape outs in 90nm and 130nm process technologies. They have a rich knowledge base in domains such as networking, multimedia processing, DSP (digital signal processing), connectivity, and wireless low power SOC design.
For more information, see http://www.tensilica.com/news_events/pr_2007_06_19.htm
Thursday, June 14, 2007
“In the PHY, the powerful Xtensa LX2 DSP core enables the implementation of various MIMO receiver configurations. In the MAC layer, the Xtensa LX2 processors are the engine of the embedded high packet rate network processor, forming a highly-configurable design to track the future 802.16e standard evolution, as well as the emerging 802.16j standard. The robustness and sophistication of the Xtensa toolset allowed us to have packets traversing an RTL simulation on day 2 of the development effort. Today, these multi-core subsystems are up and running on the FPGA boards in our integration labs, with several months of testing already completed.”
For more information, see http://www.tensilica.com/news_events/pr_2007_06_14.htm
Tuesday, June 12, 2007
Friday, June 08, 2007
Thursday, June 07, 2007
This 5.7 MHz requirement includes the entire MP3 decode functionality, including MPEG container parsing and variable length decoding (VLD, also known as Huffman decoding). Some competing offerings are merely accelerator blocks that exclude portions of the complex control code in MP3 such as VLD, and thus rely on a processor to perform VLD decoding. Tensilica’s 5.7 MHz figure is all inclusive.
For more information, see http://www.tensilica.com/news_events/pr_2007_05_16.htm
The KAIST (Korea Advanced Institute of Science and Technology) has licensed Xtensa to develop multimedia SOC designs.
Our agreement with these two universities underscores our dedication to working with universities around the world to train next-generation design engineers. We now have over 80 universities worldwide that use Xtensa processors in their research and/or classrooms.
Friday, May 11, 2007
Tuesday, May 08, 2007
For more information, see http://www.tensilica.com/news_events/pr_2007_05_08.htm
Tuesday, April 17, 2007
Tuesday, April 03, 2007
CMC Microsystems Provides Hundreds of Canadian University Researchers with Access to Tensilica Prototyping Technology for Designs Using Xtensa LX2
This technology, which helps optimize designs by reducing the power and increasing the efficiency of the chip, will enable engineers at 36 participating SOCRN universities to create FPGA-based hardware prototypes for designs that include customized versions of the Xtensa LX2 processor. The agreement will enable wider use and application of system-on-chip (SOC) designs with Tensilica’s Xtensa-based configurable processor technology.
For more information, see http://www.tensilica.com/news_events/pr_2007_04_03.htm
Tuesday, March 27, 2007
Friday, March 09, 2007
“Our chips deliver outstanding picture quality, and now we can also deliver exceptional audio quality with Tensilica’s HiFi 2 Audio Engine,” stated Chip Burczak, CEO of Enuclia. “We were impressed with the HiFi 2 Audio Engine because of its small size and the ability to run codecs more efficiently than competing solutions. Tensilica has been a solid partner for Enuclia.”
For more information, see http://www.tensilica.com/news_events/pr_2007_03_06.htm
Craig Lytle, Stretch President and CEO commented; “The ability to accelerate a target application for the Xtensa processor through the creation of Tensilica Instruction Extensions in real time, is key to achieving the breakthrough performance levels needed by today’s demanding audio/video processing applications. We are delighted to be extending our relationship with Tensilica into our new S6000 family and are tremendously excited about the performance levels we have been able to deliver in this platform.”
For more information, see http://www.tensilica.com/news_events/pr_2007_03_05.htm
Tuesday, February 27, 2007
“Xenergy will naturally appeal to designers of portable, battery-driven devices such as cellular phones and personal media players, but also to designers of complex SOCs in home entertainment and networking devices where heat is becoming a huge issue,” stated Chris Rowen, Tensilica’s president and CEO. “Tensilica is the first company to provide a realistic way to easily estimate the overall energy impact of different processor configurations and extensions together with application code tuning on each processor with its memory subsystem. The improvement in power at the architectural level is quite dramatic and productive, often dwarfing the power savings painfully achieved at the RTL and physical design levels.”
For more information, see http://www.tensilica.com/news_events/pr_2007_02_26.htm
Friday, February 23, 2007
For more information, see http://www.tensilica.com/news_events/pr_2007_02_13.htm
“We needed the flexibility of a small 32-bit processor core for the evolving requirements of the 10 Gbps PHY market,” stated Pirooz Hojabri, vice president of engineering, Plato Networks. “The Diamond Standard 108Mini was the perfect fit from a size, power, code density, and cost perspective.”
For more information, see http://www.tensilica.com/news_events/pr_2007_02_12.htm
Wednesday, February 07, 2007
For more information, see http://www.tensilica.com/news_events/pr_2007_02_07.htm
Tuesday, February 06, 2007
“AM3D’s 3D audio products provide outstanding audio quality, 3D and special effects for mobile phones and portable music players,” stated Larry Przywara, Tensilica’s director of mobile multimedia products. “By adding AM3D’s audio software to our HiFi 2 product line, we can provide one programmable engine that runs all of the best-in-class audio software.”
For more information, see http://www.tensilica.com/news_events/pr_2007_02_06.htm
Monday, February 05, 2007
LG Electronics Licenses Tensilica’s Diamond Standard 330HiFi For High Quality Audio in Mobile TV Chipset
LG Electronics currently uses Tensilica’s Xtensa processors for video and control processing in their Terrestrial Digital Multimedia Broadcasting (T-DMB) phone.
“We picked Tensilica’s Diamond Standard 330HiFi Audio Engine for three main reasons: low power, availability of a wide range of audio codecs, and our strong relationship with Tensilica’s technology in our DMB group,” stated Dr. Woo-Hyun Paik, Vice President of LG. “Tensilica’s Audio Engine is a proven solution, ready to drop into our next-generation designs.”
For more information, see http://www.tensilica.com/news_events/pr_2007_02_05_LG.htm
“S2C will be a valuable partner in helping us speed up the adoption of our Diamond Standard processors in China,” stated Steve Roddy, Tensilica’s vice president of marketing. “Customers will be able to rapidly evaluate and implement our processor cores into their SOC prototypes that can run at near-real time and real time speeds and accelerate hardware/software co-design.”
For more information, see http://www.tensilica.com/news_events/pr_2007_02_05_S2C.htm
Thursday, February 01, 2007
“By using Tensilica’s Xtensa processors in three very high-volume product lines, Marvell is able to take advantage of the extreme flexibility that these configurable processors provide for our design teams,” stated Alan Armstrong, vice president of marketing for Marvell’s Storage Business Group. “Our design teams will be able to deploy Tensilica processors in a broad range of roles, including many non-traditional design sockets within datapath and dataplane functions.”
For more information, see http://www.tensilica.com/news_events/pr_2007_02_01.htm
Wednesday, January 31, 2007
For more information, see http://www.tensilica.com/news_events/pr_2007_01_31.htm
Tuesday, January 30, 2007
Epson’s engineers added Tensilica Instruction Extensions (TIE ) to customize several different Xtensa LX processors, each for a unique step in the inkjet image processing chain. By utilizing unique features of the Xtensa LX processor which allow direct high-speed data communication between the processors and thereby avoid the time delays of bus-based data traffic, Epson’s engineers were able to reduce the time required to print a single page to less than a third of that required by previous generation inkjet printers. These new printers can print borderless 4 x 6 photos as fast as the highest printing speed for black and white text.
For more information on this interesting application, see http://www.tensilica.com/news_events/pr_2007_01_30_Epson.htm
“Sony’s engineers realize the value of using a configurable processor to lower power and significantly improve performance in hand-held, battery powered devices,” stated Chris Rowen, Tensilica’s president and CEO. “We expect the Xtensa LX2 processor core will be used in designing Sony’s future consumer product and look forward to working with them on their next-generation design projects.”
Tuesday, January 23, 2007
Design engineers can now use CoWare’s Platform Architect ESL environment to do full architectural exploration, design verification, and software development when designing with Tensilica’s Diamond Standard processors and Tensilica’s highly-configurable Xtensa processors. This collaboration provides a huge productivity boost for SoC designers, as it not only speeds the design process, but also enables parallel development of the hardware and software.
For more information, see http://www.tensilica.com/news_events/pr_2007_01_23.htm
Monday, January 22, 2007
Tensilica Introduces TurboXim Fast Functional Simulator 40-80x Faster than ISS, Automatic SystemC Model Generation
Tensilica also introduced its ability to automatically generate SystemC models to match all possible configurations of its Xtensa configurable processors and Diamond Standard series processors.
These introductions significantly speed ESL (embedded system level) design and architectural exploration for SOC (system-on-chip) design using one or more Xtensa configurable processors or Diamond Standard processors.
For more information, see http://www.tensilica.com/news_events/pr_2007_01_22.htm
Friday, January 19, 2007
The seminar will open with a presentation from The Linley Group highlighting recent trends in intellectual property. The program includes a session on CPU cores for ASICs and SOCs, featuring presentations on how to get the most out of popular ARM, MIPS, Power, and Tensilica CPUs. The event also includes a session on other IP for networking, including security, high-speed interfaces, and wireless technology. We have an outstanding lineup of speakers and talks, including:
Sumit Gupta, a product marketing manager at Tensilica, will present "Networking Applications for Xtensa Configurable CPU Cores."
This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Register now to guarantee your place. The seminar is targeted at ASIC and SoC designers, OEMs, press, and the financial community. Your free attendance is made possible by our event sponsors: Freescale, Tensilica, SafeNet, MIPS, Rambus, IBM, and ARM. Sign up now at: http://www.linleygroup.com/seminars.html
Tuesday, January 16, 2007
January 24, 2007 - 11 am PST/2 pm EST - Register Now!
Join Virage Logic and Tensilica for an informative technical webinar on the recently introduced Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family. Specifically tuned to optimize the performance of Tensilica's Diamond Standard product line processor cores, this joint collaboration provides mutual customers with physical IP that leverages Virage Logic's silicon proven embedded memory IP and standard cell libraries to meet a variety of market requirements. The Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores on TSMC’s 130-nanometer (nm) and 90nm G processes.
Learn how customers can utilize easy instant access to a series of jointly-developed Core-Optimized IP Kits specifically optimized for each of the Diamond cores that allows designers to target area, performance or power for a greater competitive advantage.
You won't want to miss this exclusive technical webinar where Virage Logic and Tensilica will jointly provide an overview of the Core-Optimized IP Kits and then show how Virage Logic's highly differentiated, silicon proven semiconductor IP has been optimized specifically to enhance Tensilica’s Diamond Standard processor cores.
Thursday, January 11, 2007
According to Portable Design, “Every year Portable Design reviews several hundred products intended to make life easier for designers of portable electronic devices... We recognize the best of the best with our 2006 Editor's Choice Award. We believe that these products are indicative of the creativity our readers bring to bear, and they're worthy of the wider recognition that this award will bring."
See Portable Design's Editor's Choice award recipients.