Follow us on:
Subscribe Twitter Facebook

Tuesday, November 30, 2010

Tensilica CTO Chris Rowen Presents at SDR'10 Thursday

Chris Rowen, Tensilica founder and chief technology officer, has been invited to present "Extensible Baseband DSPs, Tools and Multi-Core Architectures for Low-Power 4G SDR Silicon Platforms" at the upcoming SDR'10 event in Washington, D.C. SDR'10 focuses on reconfigurable radio technologies and Rowen's presentation will highlight Tensilica's second generation processor-based, multi-standard handset baseband reference architecture.

In addition, Rowen will participate in a panel discussion on "Comparing FPGA + C compilers with Multi-core Technology." This panel will look at the costs, programmability, performance, power, and time-to-market of multiprocessor designs versus FPGAs to see who will ultimately dominate future SDR platforms.

"Extensible Baseband DSPs, Tools and Multi-Core Architectures for Low-Power 4G SDR Silicon Platforms"
Thursday, Dec. 2 at 3:25 p.m., Section 6A, Applications

"Comparing FPGA + C Compilers with Multi-core Technology"
Thursday, Dec. 2 at 5:10 p.m., Panel Session

SDR'10 will be held at the Hyatt Regency Crystal City in Washington, D.C. For more information, visit

Wednesday, November 24, 2010

Happy Thanksgiving Everyone

Tensilica's US offices will be closed tomorrow and Friday. We'll be giving thanks for another good year and all the wonderful Thanksgiving food we'll be eating. We'll be back Monday, probably a pound or two heavier.

Monday, November 22, 2010

White Paper: How to Increase ASIC Performance with Long-Word Processors

By packing multiple operations into a wide 32- or 64-bit instruction word, FLIX technology allows designers to accelerate a broader class of “hot spots" in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.

Thursday, November 18, 2010

White Paper on TIE - Tensilica Instructin Extensions

TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces. TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power. Read the white paper to find out more.

Monday, November 15, 2010

New Job Posting: Sr. Strategic Field Application Engineer

We are looking for someone who can work directly with customers in key technical pre-sales and post-sales roles to provide architectural and design consulting on the best use of Xtensa in a customer's ASIC design.

Friday, November 12, 2010

Have You Seen all the Smart Phones with Tensilica Inside?

The Samsung Capitvate and Ruby II, the Google Nexus One, the LG SH-400, the Sharp SH705ill, the Pantech Ease and Hush - see them by clicking on the headline.

Wednesday, November 10, 2010

White paper: Highest MHz Does Not Mean Highest Peformance

In fact, processors with high clock rates consume much more power because power dissipation rises faster than operating frequency. All major PC CPU vendors now offer multicore processors that run at lower clock frequencies than older generation single-core processors.

The same argument holds true for embedded processors, which is even more important for embedded products that operate under very tight power/energy budgets such as portable devices-because extending battery life is an important feature that improves product marketability-but it is also true for non-portable devices because consumers do not want noisy cooling fans in their set-top boxs or flt-panel televisions while IT managers want routers and switches that reduce electrical costs by minimizing energy consumption in the data centers. For these reasons, SOC development teams need to achieve performance goals while keeping a lid on clock rates.

Monday, November 08, 2010

Featured partner: Dolby Labs

Tensilica's HiFi 2 and HiFi EP Audio DSPs provide the widest range of support for the excellent software Dolby has to offer for home entertainment. See our complete list of codecs.

Friday, November 05, 2010

Happy Diwali

For our employees and friends in India, happy Diwali.

Thursday, November 04, 2010

Cut DSP Development Time - Get High Performance from C - Read our White Paper

The magic is in the compiler technology. Learn how an advanced compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code.

Tuesday, November 02, 2010

Will Google TV be a Winner?

Yes, Tensilica's audio is designed into Google TV. But we're not the only ones who think Google TV will be a great platform. See this discussion.

Monday, November 01, 2010

White Paper: A PRocessor and DSP IP Selection Checklist

Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle.