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Wednesday, August 26, 2009

Tata Elxsi's DSP SW Runs on ConnX D2 DSP

Tensilica has tested optimized C source code from Tata Elxsi's extensive DSP software library and the existing code - including code optimized with industry standard C intrinsics - ran flawlessly on Tensilica's new ConnX D2 DSP engine. This means that designers can rely on Tata Elxsi's proven software services to quickly get new ConnX D2-based SOCs designed into innovative new products. This also means that other C code with intrinsics should work just fine on the ConnX D2 DSP.

Tuesday, August 25, 2009

New White Paper: Cut DSP Development Time

The magic is in the compiler technology. Learn how an advanced compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code.

Monday, August 24, 2009

ConnX D2 DSP Engine Combines Outstanding Performance, Compact Size, and Easy Programmability

New today - the high-performance, small, low-power ConnX D2 16-bit dual-MAC DSP engine for SOC designs. The ConnX D2 DSP engine provides uncompromised performance from C code, unlike many other DSPs that require time consuming assembly coding for maximum performance. This means that virtually any C program, including those written with C intrinsic functions for the TI C6x family or ITU (International Telecommunications Union) reference code, can run unmodified and with excellent performance on the ConnX D2 DSP engine. Find out more at

Thursday, August 20, 2009

Apnote: Multiple Audio Codec Operation

This application note describes a multi-stream audio decoder test bench that works without needing a threading operating system. A software test bench is provided for the Diamond 330HiFi processor that supports decoding and audio mixing of an arbitrary number of homogenous or heterogeneous audio streams. This application note describes the test bench, and discusses the coding techniques used to reduce memory requirements and to synchronize/mix audio decoded from multiple streams.

Friday, August 14, 2009

New Ap Note on TIE Ports

Why do so many designers pick Tensilica's Xtensa LX? TIE Ports are an important part of the answer. They let you bypass the bus and connect directly, much like GPIO. Read this application note and find out how you can significantly increase I/O speed, unlike any other processor core.

Tuesday, August 11, 2009

Microprocessor Report Reviews ConnX Baseband Engine

See the 9-page in-depth review of Tensilica's new ConnX Baseband Engine written by Tom Halfill of Microprocessor Report ( If you are not a subscriber, email for your free pdf of this important review.

Tuesday, August 04, 2009

White Paper on Digital Audio

Whitepaper: Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

Digital audio has rocketed to the top of the critical features list for all sorts of products over the past several years. At the same time, the number of digital audio codecs and audio-enhancement programs has exploded. Now most consumer products must support multiple codecs and offer a broad range of audio-enhancement features.

This has created high demand for a flexible, high-performance, low-power audio engine that adds sound to an SOC's design with the least amount of design effort and a small on-chip footprint. Tensilica's HiFi 2 Audio Engine was carefully crafted to meet the requirements for the broadest possible range of consumer products, from mobile music players to in-home high-end entertainment centers. Read the white paper:

Monday, August 03, 2009

Ap note: Implementing the Advanced Encryption Standard on Xtensa Processors

This application note examines the Advanced Encryption Standard (AES) cipher and illustrates the power of a configurable processor in accelerating encryption and decryption. Xtensa-based application-specific processors are quickly designed, simulated, and instantiated in silicon. These processors offer performance that rivals hardware solutions along with the benefits of flexibility, programmability, and ease of verification found with purely software implementations. The processor extensions proposed in this application note give the Xtensa processor a speedup of over 300x compared to a base Xtensa processor or a similar 32-bit RISC engine such as ARM9, MIPS32, etc. See

Tensilica Great Race Results

Tensilica great race results: First place: Brian Withers. Second place: Jack Guedj. Third place: Stuart Fiske - the prize? A bottle of Champaigne - the drink of champions