Friday, March 26, 2010
White paper: Get your ASICs off the Bus
Bypass the bus altogether with GPIO and FIFO-like interfaces from Tensilica's processor cores. Read about how this significantly speeds data through the processor in this white paper.
All the news you're looking for from Tensilica, Inc. Find out how you can use Tensilica's customizable, extensible processors to speed your SOC design. See Tensilica for DSPs and all the processing you need to do in the dataplane (dataplane processors - DPUs).