Follow us on:
Subscribe Twitter Facebook

Tuesday, January 16, 2007

Virage Logic - Tensilica Net Seminar

Optimize Area, Performance or Power with Tensilica and Virage Logic Core-Optimized IP Kits
January 24, 2007 - 11 am PST/2 pm EST - Register Now!

Join Virage Logic and Tensilica for an informative technical webinar on the recently introduced Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family. Specifically tuned to optimize the performance of Tensilica's Diamond Standard product line processor cores, this joint collaboration provides mutual customers with physical IP that leverages Virage Logic's silicon proven embedded memory IP and standard cell libraries to meet a variety of market requirements. The Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores on TSMC’s 130-nanometer (nm) and 90nm G processes.

Learn how customers can utilize easy instant access to a series of jointly-developed Core-Optimized IP Kits specifically optimized for each of the Diamond cores that allows designers to target area, performance or power for a greater competitive advantage.

You won't want to miss this exclusive technical webinar where Virage Logic and Tensilica will jointly provide an overview of the Core-Optimized IP Kits and then show how Virage Logic's highly differentiated, silicon proven semiconductor IP has been optimized specifically to enhance Tensilica’s Diamond Standard processor cores.

No comments: