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Wednesday, June 20, 2007

Tensilica Enhances Reference Flow with Cadence Encounter RTL Compiler

Tensilica incorporated Cadence Encounter RTL Compiler with global synthesis in its CAD flow which supports both Diamond and Xtensa cores. Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP.

With the RTL Compiler multi-objective optimization, customers can achieve significant advantages in area, speed and performance. In tests, Tensilica achieved a 10 percent increase in speed and a reduction of cell area of 5 percent. The RTL Compiler global synthesis solution improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.

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