New Dolby Digital Consumer Encoder and Dolby Digital Compatible Output 5.1-Channel Encoders

Tensilica has added the Dolby Digital Consumer Encoder (DDCE) and Dolby Digital Compatible Output (DDCO) 5.1-channel encoders to its audio codec library for the Xtensa HiFi 2 Audio Engine, one of the most popular commercial audio cores for system-on-chip (SOC) designs. These encoders enable manufacturers to design consumer devices, including Blu-ray Disc players, HD DVD players, portable devices and camcorders, which support Dolby 5.1-channel surround sound as well as next-generation high-definition (HD) video technologies.

For more information, see http://www.tensilica.com/news_events/pr_2007_12_18.htm

Tensilica Enhances Xtensa Configurable Processor Families

Tensilica has upgraded its two Xtensa configurable processor families (the Xtensa 7 and Xtensa LX2) with new hardware options and software tool enhancements that make it appeal to an even wider audience of SOC (system-on-chip) designers. Highlights of these capabilities include a new, smaller general purpose register file option, new integer multiplier and divider execution unit options, two new AMBA (Advanced Microcontroller Bus Architecture 3.0) bridge options, as well as an easy-to-use new configuration tool that analyzes source C/C++ code and automatically suggests VLIW (very long instruction word) instruction extensions that lead to 30-60 percent improvements in general purpose code performance.

These new capabilities provide designers with the most productive configurable processor design environment, with automated features that ensure each processor design is correct by construction. For more information, see http://www.tensilica.com/news_events/pr_2007_12_10_xtensa.htm

New Integrated Real-Time Trace Support

Tensilica has added an optional full-speed, non-intrusive instruction trace capability to all of its Diamond Standard and Xtensa configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAX-PC trace macrocell.

For more information, see http://www.tensilica.com/news_events/pr_2007_12_10_trax.htm

NEC Electronics America Offers Free License for Tensilica's Diamond Standard 106Micro Processor Core

NEC Electronics America, Inc. will offer a free license for Tensilica's Diamond Standard 106Micro processor core used in NEC Electronics gate arrays to attendees of a co-sponsored webcast seminar with Tensilica, Inc. This offer, valued from $25,000 to $75,000, is valid through March 31, 2008, upon receipt of a signed purchase order.

To join the webcast, go to:https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=97638&sessionid=1&key=F68674417431BD07F49139A0A29B605B&partnerref =evite1&sourcepage=register. For those unable to attend the livewebcast, it will be available on demand for one year.

Express Logic Introduces ThreadX RTOS Support for Diamond Standard 106Micro

Express Logic announced ThreadX RTOS and middleware support for Tensilica’s new Diamond Standard 106Micro 32-bit microcontroller core. ThreadX supports the entire line of Tensilica’s Xtensa configurable cores, and its Diamond Standard series of preconfigured cores. The addition of the 106Micro continues ThreadX support for the complete Tensilica processor family.

ThreadX is Express Logic’s small, fast, royalty-free RTOS for demanding real-time applications. Its royalty-free business model makes ThreadX extremely attractive for high-volume devices. ThreadX’s ease-of-use enables ThreadX-powered devices to get to market on time and within budget, which accounts for ThreadX’s success in the marketplace and its high-volume implementations. ThreadX has been widely embraced and is currently deployed in excess of 450 million electronic products. ThreadX is complemented by Express Logic’s NetX TCP/IP stack, FileX file system, USBX USB stack, and PEGX GUI development kit, all of which also are available for Tensilica’s new Diamond Standard 106Micro.

For more information, see http://www.tensilica.com/news_events/pr_2007_12_3.htm

DS2 Licenses Tensilica’s Xtensa Processor for 200 Mbps Powerline Chipset

Design of Systems on Silicon S.A. (DS2) has licensed Tensilica’s Xtensa configurable processor to use as a controller in a 200 Mbps powerline chipset. This chipset enables broadband and networking in homes over power lines, coaxial cable and telephone wire.

“We needed a supplier we could depend on, and we were very impressed with Tensilica’s support for their products,” stated Mayte Bacete, operations director, DS2. “The Xtensa configurable processor gives us the right mix of performance and low power that we need for these chip designs.”

See the full press release at http://www.tensilica.com/news_events/pr_2007_11_28.htm

eASIC and Tensilica Partnership Delivers Free Diamond Processors on Free Mask Charge ASIC

Tensilica and eASIC announced a partnership to remove the cost barriers for developing custom embedded System-on-a-Chip (SoCs). Through this partnership eASIC now provides free access to Tensilica’s Diamond Standard microprocessor and digital signal processing (DSP) cores for its free mask charge, no-minimum order ASICs. This unique combination enables embedded system designers to develop Diamond processor-based SoCs for applications in any production volume. Designers will now be able to develop customized, highly differentiated ASIC solutions at a lower cost than FPGA-based embedded systems.

For more information, see http://www.tensilica.com/news_events/pr_2007_11_26.htm

CoWare and Tensilica Integrate Diamond Standard 106Micro with CoWare ESL 2.0 Technology

Tensilica processor integration enables development of better products faster through the use of CoWare Platform Architect for platform architecture design, platform verificationand software development.

By integrating Tensilica’s Diamond Standard 106Micro, the smallest licensable 32-bit processor core, with CoWare Platform Architect, designers get the first and most productive ESL 2.0 solution for platform architecture design, platform verification, and software development using Tensilica’s processor cores.

For more information: http://www.tensilica.com/news_events/pr_2007_11_20.htm

DTS Audio Technologies for Blu-ray Disc and HD DVD to be Added to Tensilica’s HiFi 2 Audio Engine

Tensilica will provide leading-edge DTS technologies for both Blu-ray Disc and HD DVD and other high end consumer audio applications with Tensilica’s HiFi 2 Audio Engine, the most popular commercial audio DSP core for system-on-chip (SOC) designs.

“By working with Tensilica, we can help our customers incorporate our advanced sound technologies very quickly and easily,” stated Brian Towne, Senior Vice President and General Manager, Consumer Division at DTS. “The market for high definition audio systems is beginning to materialize and the availability of DTS technologies on the HiFi 2 audio engine will help enable the accelerating growth.”

For more information: http://www.tensilica.com/news_events/pr_2007_11_13.htm

Diamond Standard 106Micro Processor is Smallest Licensable 32-bit Core

Tensilica unveiled the industry's smallest licensable 32-bit processor core based on an industry-standard architecture. The new Diamond Standard 106Micro core takes up only 0.26 mm2 in a 130-nm G process and only 0.13 mm2 in a 90-nm G process, which makes it smaller than the ARM7 or Cortex-M3 cores, yet at 1.22 Dhrystone MIPS/MHz, it delivers higher performance than the ARM9E cores.

The low-power Diamond Standard 106Micro is designed for simple controller applications in SOC (system-on-chip) designs, and an ideal choice for designers migrating from 8-bit and 16-bit microcontrollers to 32-bit processors. All Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners, who provide support with operating systems, design services, hardware prototyping and emulation, libraries and memories, EDA tools, and peripherals. For more information, see http://www.tensilica.com/news_events/pr_2007_11_05_106.htm

Entire Diamond Standard Processor Core Family Enhanced

Tensilica enhanced its successful Diamond Standard processor product line, the lowest-power, most area-efficient and highest-performance licensable cores on the market. The new second-generation Diamond Standard processors include several new features including additional multiplier and divider functional units, several hardware optimizations that lower memory power by up to 30 percent, and an optional bridge to AXI-based AMBA systems. For more information, see http://www.tensilica.com/news_events/pr_2007_11_05_diamonds.htm

Valens Semiconductor Picks Diamond Standard 108Mini for chip that Ensures High-Quality Home Audio-Video Networking

Valens Semiconductor, an Israeli start-up, has selected the Diamond Standard 108Mini as the controller for a SOC (system-on-chip) design that will enable high-quality transmission of audio and video in a home networking environment. “We are designing a chip that will enable high quality transmission of audio and video in a home networking environment,” stated Dror Jerushalmi, CEO of Valens. “We picked the Diamond Standard 108Mini as our central controller based on the high quality Diamond Standard software tool environment, the low-power advantages of the Diamond 108Mini processor compared to conventional alternatives, and because the Diamond 108Mini core had the performance-headroom we needed.”

For more information, see http://www.tensilica.com/news_events/pr_2007_10_31.htm

MediaPhy Licenses Tensilica's Diamond Standard 108Mini Processor Core

MediaPhy Corporation, of San Jose, Calif., has licensed the Diamond Standard 108Mini, the industry’s lowest power 32-bit processor core for SOC (system-on-chip) design. MediaPhy will use the Diamond Standard 108Mini in its next generation mobile audio and video entertainment designs.

“One of our main target application areas is battery operated mobile/portable devices where power consumption is a very critical factor.” stated Mohammad Moradi, Co-Founder and Executive VP of Engineering at MediaPhy. “As such, we have chosen the Tensilica Diamond Standard 108Mini processor core to benefit from its low power consumption and small area at the same time.”

Tensilica Picks EVE's ZeBu for Validation of Diamond Video Core

Tensilica used EVE’s ZeBu to validate the Diamond 38xVDO Video Engines. Targeted at mobile handsets and personal media players (PMPs), Tensilica’s Diamond Standard Video Engines are fully programmable to support VGA and standard definition (SD, also known as D1) video codecs.

ZeBu (for Zero Bugs) gives Tensilica verification engineers an easy-to-use and affordable solution that combines the best aspects of traditional emulation and rapid prototyping systems. It is used in Tensilica’s system-level regression testing, hardware/software integration, application and codec development, conformance testing and profiling. ZeBu also proved useful in validating multi-processor synchronous debugging. In addition to allowing software engineers to validate codecs, ZeBu also helped Tensilica’s engineers find subtle bugs during product development related to clock tree issues missed during register transfer level (RTL) simulation.

For more information, see http://www.tensilica.com/news_events/pr_2007_09_18.htm

Tensilica Joins Chip Estimate's Prime IP Partner Program

As a Prime IP Partner, Tensilica is enabling centralized access to information about the company’s standard processor cores and configurable processor technology at ChipEstimate.com. Tensilica IP solutions for system-on-chip (SOC) designs allow designers to create lower power, higher performance hardware and software for their integrated circuits.

ChipEstimate.com was launched in 2005 to provide comprehensive chip planning capabilities to the electronics and semiconductor community. In addition to the comprehensive IP catalog, designers can use the InCyte software available through the website to plan their next chips and explore die size, power, leakage and cost tradeoffs. Tensilica IP can now be searched for and considered in chip estimations though the portal.

A complete list of Chip Estimate IP partners can be seen at http://www.chipestimate.com/vendorlist.php.

P-Product Ports Codecs to the HiFi 2 Audio Engine

“Customers interested in custom ports of specialized audio codecs can turn to P-Product because they have the expertise in programming Tensilica's HiFi 2 Audio Engine platform,” stated Larry Przywara, Tensilica's director of mobile multimedia. “With their porting and algorithm optimization experience, P-Product is a strong asset for our HiFi 2 customers.”

“The HiFi 2 Audio Engine is a very well optimized core for all audio functions, ranging from low-power MP3 to high-end surround sound,” stated Michael Vulikh, CEO of P-Product. “The audio centric instructions Tensilica created enable easy programming in C code, avoiding the time consuming assembly-level programming usually required when porting audio algorithms to the typical DSPs and CPUs. The HiFi2 audio engine allows us to deliver superior MHz performance with far less development effort.”

P-Product has already ported audio software to Tensilica's HiFi 2 Audio Engine and has significant expertise in audio and video software porting.

Webcast this Wednesday

Tensilica will present a live webcast, “Using Configurable Processors as Enhanced
Application Processors and Controllers,” highlighting the way for SOC (system on chip) designers to achieve high performance while keeping the processor core area very small. The seminar will show the process of evaluating code for hot spots and then accelerlerating those functions using configuration options and the Verilog-like Tensilica Instruction Extension (TIE) language.

This webcast is Wednesday, September 12, at 11:00 a.m. PT / 2 p.m. ET. Sign up here: https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=92084&sessionid=1&key=477F1AD28B50C3D5E0FA6677040660D1&partnerref=sponlink&sourcepage=register

Tensilica and Tallika Announce Secure SOC FPGA Platform

The Configurable Secure SOC FPGA/ASIC Platform, based on Tensilica’s Xtensa Processor, is a fully verified and silicon proven hardware/software platform that is ideal for any design team that needs a full implementation of RSA (including encryption, decryption, and key-pair generation acceleration) and/or an SOC with integrated hardware security functions.
Tallika’s security solution includes a 32-bit AHB/APB backbone and Tallika’s linked-list-based DMA controller integrated with its security IP blocks - AES/TDES/SHA/MD5 on the AHB bus and 2048-bit native exponentiation engine on the APB bus. The Secure FPGA Platform is based on Xilinx Virtex4 LX160 FPGA devices and comes with a complete software library to access security functions as well as with a full implementation of RSA encrypt, decrypt, and key-pair generation (including acceleration for Primality testing). The solution is also available for license by Tallika as soft IP for ASIC development.

The Secure Platform core IP and FPGA platform are available now from Tallika. More information regarding this solution can be found at http://www.tallika.com/products_security_secure_soc.htm.

Buy Dell and Lenovo Notebooks with Xtensa inside

WiQuest Communications, Inc.'s WQST110/101 Certified Wireless USB silicon is being used by Dell
and Lenovo in their latest notebook PC products. Dell’s Inspiron 1720 notebook and Lenovo’s ThinkPad T61/T61p 15.4-inch widescreen notebook are part of the very first wave of Wireless USB platform certifications awarded by the USB Implementers Forum that contain WiQuest's chips, which contain Xtensa processors.

New Application Notes Available

We've posted three new application notes to our web site:
* Fast OFDM on Xtensa Processors
* Implementing A Mutex and Barrier Synchronization Library on Xtensa
* Optimizing for Energy using the Xenergy Energy Optimizator Tool

SiBEAM, Inc. Selects Tensilica Configurable Processor for Baseband DSP in Wireless Link for HDTV Devices

SiBEAM, Inc., a leading innovator of millimeter wave (mmWave) solutions and developer of high-speed wireless communications platforms, has selected Tensilica’s Xtensa configurable processor for an upcoming chip design project.for baseband DSP.

“SiBEAM has developed its wireless communications products to deliver high quality wireless video solutions for consumer electronics and display applications. These applications demand high data rate transmission to multiple devices within an indoor wireless environment using conventional CMOS silicon,” said Kumar Mahesh, manager of MAC and Software Design for SiBEAM, Inc. “We selected Tensilica’s Xtensa processor for its ability to help us achieve our goal of developing innovative-multi-gigabit, lower-power mmWave communications products. By optimizing the Xtensa processor into a tailored processor core, this enables our products to attain the performance these wireless applications demand.”

For more information, see http://www.tensilica.com/news_events/pr_2007_08_20.htm

See Audio NetSeminar

Tensilica Presents
“Low-Power, Low-Overhead, High-Fidelity Digital Sound for SOCs”
Live Webcast Wednesday, August 15, at 11:00 a.m. PT

Tensilica will present a live webcast, discussing how most consumer products must support multiple codecs and offer a broad range of audio-enhancement features. All of these factors have resulted in a high demand for a flexible, high-performance, low-power audio engine that adds digital-sound capabilities to an SOC with the least amount of design effort and a small on-chip footprint. This online seminar presents a proven way to add low-power, low-overhead, high-fidelity audio to SOC designs.

The presenter for the August 15th broadcast will be Steve Leibson, Technology Evangelist, Tensilica. Leibson, the author of several books on integrated circuit design, spent 15 years as an award-winning technology journalist, serving as Editor in Chief of EDN, the Microprocessor Report, and Embedded Developers Journal. He also served as an engineer at several companies, including HP.

To sign up for this event, visit http://tensilica.com/news_events/events.htm

Tata Elxsi Becomes Tensilica's First Authorized Multimedia Processor Design Center

Tata Elxsi Ltd., a leading independent embedded design service company headquartered in Bangalore, India, with offices in major locations around the world, has become the first authorized design center for Tensilica’s multimedia customers. Tata Elxsi’s engineers have been fully trained on Tensilica’s HiFi 2 Audio Engine and Diamond Standard 38xVDO Video Engine family, and will be able to provide SOC design services including hardware and system software design for semiconductor and electronics manufacturers. Tata Elxsi has served as a design center for Tensilica’s Xtensa configurable processor family for over three years, and is already assisting global electronics companies with Tensilica-based multimedia designs.

“Tensilica’s Diamond Standard 38xVDO Video Engine family is the most capable processor core-based video solution on the market today, supplying full D1 resolution Main Profile H.264 performance,” stated Madhukar Dev, CEO, Tata Elxsi. “And the HiFi 2 Audio Engine is proven in designs that are shipping in huge volumes right now. Our turnkey SOC design capability and proven strengths in multimedia design will help Tensilica’s customers quickly integrate these powerful engines into their SOC designs, reducing product development time and costs. Our network of offices and strong presence in key geographies such as US and Europe and Asia, including Japan, Taiwan and South Korea, provides customers with easy access to world-class multimedia system and engineering expertise.”

Two NetSeminars This Week - Sign Up Now!

Tensilica will be hosting two online seminars this week. Sign up now to see them live, or watch the archived presentation afterwards:

Wednesday, July 18 - Reduce Power and Energy Consumption in Low-Power SOCs Through ISA Extension - 11 am pacific, 2 pm EST - Sign up at https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=56190&sessionid=1&key=09644E927D284A86219B1D1336A920

Thursday, July 19 - Low Cost and Low Risk 32-bit Controllers for Designing AMBA-based SOCs - 10 am pacific, 1 pm EST - Sign up at
http://www.techonline.com/learning/webinar/200001694

Tensilica Enhances Reference Flow with Cadence Encounter RTL Compiler

Tensilica incorporated Cadence Encounter RTL Compiler with global synthesis in its CAD flow which supports both Diamond and Xtensa cores. Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP.

With the RTL Compiler multi-objective optimization, customers can achieve significant advantages in area, speed and performance. In tests, Tensilica achieved a 10 percent increase in speed and a reduction of cell area of 5 percent. The RTL Compiler global synthesis solution improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.

For more information: http://www.tensilica.com/news_events/pr_2007_06_19_cadence.htm

Aftek Becomes Tensilica Configurable Processor Design Center

Aftek Limited is now an authorized Design Center partner for customers using Xtensa configurable processors, Diamond Standard Processors, and the Xtensa HiFi 2 Audio Engine in their SOC (system on chip) designs.

Aftek has considerable expertise in IP (intellectual property) integration as well as the development of system and chip specifications, hardware-software partitioning, development of reference models, and analysis of performance trade-offs. They have successful tape outs in 90nm and 130nm process technologies. They have a rich knowledge base in domains such as networking, multimedia processing, DSP (digital signal processing), connectivity, and wireless low power SOC design.

For more information, see http://www.tensilica.com/news_events/pr_2007_06_19.htm

DesignArt Networks Picks Xtensa LX2 for WiMax

“By using Tensilica’s Xtensa LX2 configurable processors in our SOC, we took our platform to a higher level of flexibility, and we are able to bring a highly configurable silicon platform to our customers. The benefits are clear – better ability of tracking customer requirements and standards evolution, as well as an in-field software upgradeable network infrastructure,” stated Oz Barak, CEO, DesignArt Networks.

“In the PHY, the powerful Xtensa LX2 DSP core enables the implementation of various MIMO receiver configurations. In the MAC layer, the Xtensa LX2 processors are the engine of the embedded high packet rate network processor, forming a highly-configurable design to track the future 802.16e standard evolution, as well as the emerging 802.16j standard. The robustness and sophistication of the Xtensa toolset allowed us to have packets traversing an RTL simulation on day 2 of the development effort. Today, these multi-core subsystems are up and running on the FPGA boards in our integration labs, with several months of testing already completed.”

For more information, see http://www.tensilica.com/news_events/pr_2007_06_14.htm

Why High MHz Does Not Mean High Performance

Do you think that high MHz = high performance? The PC industry tried to teach us that, but it simply isn't true. There are a lot of other factors, and often you can get higher performance out of an optimized lower MHz processor. See the article on SOCcentral.com at:
http://www.soccentral.com/results.asp?CatID=488&EntryID=22911

Achieving Very High Performance in the Networking Data Plane

Sign up now for Tensilica's next Techonline Seminar: Achieving Very High Performance in the Networking Data Plane. We'll be giving this seminar on Wednesdy, June 27 at 10 am Pacific time (1 pm EST). Sign up at
http://seminar2.techonline.com/registration/distrib.cgi?s=1096&d=1062

Tensilica Announces Industry’s First MP3 Decoder Under 6 MHz

Tensilica has optimized the MP3 decoder for its Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. This MP3 decoder now runs at the lowest power and is the most efficient in the industry, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65nm LP process (including memories). This makes Tensilica’s Xtensa HiFi 2 Audio Engine ideal for adding MP3 playback to cellular phones, where current carrier requirements are for 100 hours of playback time on a battery charge, and increasing to 200 hours in the near future.

This 5.7 MHz requirement includes the entire MP3 decode functionality, including MPEG container parsing and variable length decoding (VLD, also known as Huffman decoding). Some competing offerings are merely accelerator blocks that exclude portions of the complex control code in MP3 such as VLD, and thus rely on a processor to perform VLD decoding. Tensilica’s 5.7 MHz figure is all inclusive.

For more information, see http://www.tensilica.com/news_events/pr_2007_05_16.htm

Two Korean Universities License Xtensa

The CoSoC (Center of System on Chip design technology) of Seoul National University is using Xtensa processors in the classroom and has announced their third annual SOC design contest, which will, for the first timie, accept designs that use Xtensa processors.

The KAIST (Korea Advanced Institute of Science and Technology) has licensed Xtensa to develop multimedia SOC designs.

Our agreement with these two universities underscores our dedication to working with universities around the world to train next-generation design engineers. We now have over 80 universities worldwide that use Xtensa processors in their research and/or classrooms.

Great new article on our video processor

Find out what's inside the Diamond Video Engine for encoding/decoding H.264/AVC video. Video/Imaging DesignLine.com posted Steve Leibson's article "Anatomy of a hardware video codec" today at http://www.videsignline.com/howto/videoprocessing/199500920.

SRS Labs Ports TruSurround HD for HDTV

SRS Labs has ported its TruSurround HD virtual sound audio technology to Tensilica’s HiFi 2 Audio Engine for Xtensa processors and the Diamond Standard 330HiFi Audio Processor. SRS TruSurround HD is ideal for designers of system-on-chip (SOC) devices for the midrange and high-end digital television and digital home entertainment markets. Tensilica’s HiFi 2 Audio Engine is the most popular commercial audio processor core for SOC designs, and this year Tensilica’s customers are forecasting they will ship 100 million HiFi Audio Engine enabled processor cores in a wide variety of consumer devices.
For more information, see http://www.tensilica.com/news_events/pr_2007_05_08.htm

Commetrex Fax Solutions Now Available

Commetrex’ fax technologies now support Tensilica’s Xtensa configurable and Diamond Standard processor cores. This proven solution, already shipping in high volume, will give Tensilica’s customers a complete, off-the-shelf solution for products requiring built-in fax capabilities. For more information, see http://www.tensilica.com/news_events/pr_2007_05_02.htm

Tensilica Adds Support for Low-Cost, Hardware-Based Simulations of Diamond Standard Processors

Tensilica is now supporting Avnet LX60 FPGA boards for high-speed hardware-based simulations of its Diamond Standard processor family. Software developers can use these popular, very-low-cost FPGA boards, which allow Diamond Standard processor cores to run on Xilinx Virtex-4 FPGAs, to speed their software design, debug and program optimization processes. For more information, see http://www.tensilica.com/news_events/pr_2007_04_17.htm

CMC Microsystems Provides Hundreds of Canadian University Researchers with Access to Tensilica Prototyping Technology for Designs Using Xtensa LX2

CMC Microsystems has upgraded its license for Tensilica’s Xtensa LX2 processor generator, boosting the prototyping capability available to university researchers through Canada’s System-on-Chip Research Network (SOCRN).

This technology, which helps optimize designs by reducing the power and increasing the efficiency of the chip, will enable engineers at 36 participating SOCRN universities to create FPGA-based hardware prototypes for designs that include customized versions of the Xtensa LX2 processor. The agreement will enable wider use and application of system-on-chip (SOC) designs with Tensilica’s Xtensa-based configurable processor technology.

For more information, see http://www.tensilica.com/news_events/pr_2007_04_03.htm

ByteTools’ Low-Cost Catapult Probe Supports Tensilica’s Processors

ByteTools’ Catapult JTAG probes are now available for Tensilica’s Diamond Standard and Xtensa configurable processors. The high-performance, low-cost Catapult devices work out-of-the-box with Tensilica’s software development tools, meaning that users need not install any additional software. Catapult probes interface to the standard XOCD 14-pin JTAG header, with Catapult EJ-1 offering an Ethernet host interface, and Catapult UJ-1 offering a USB host interface. For more information, see http://www.tensilica.com/news_events/pr_2007_03_27.htm

Enuclia Picks Tensilica’s HiFi 2 Audio Engine for Flat Panel TV Chips

Enuclia Semiconductorselected the Xtensa LX processor with the HiFi 2 Audio Engine for its next-generation flat-panel TV integrated circuits. Enuclia is developing chips that produce the best possible picture on analog and digital televisions whether they are displaying standard or high-definition content.

“Our chips deliver outstanding picture quality, and now we can also deliver exceptional audio quality with Tensilica’s HiFi 2 Audio Engine,” stated Chip Burczak, CEO of Enuclia. “We were impressed with the HiFi 2 Audio Engine because of its small size and the ability to run codecs more efficiently than competing solutions. Tensilica has been a solid partner for Enuclia.”

For more information, see http://www.tensilica.com/news_events/pr_2007_03_06.htm

Stretch Selects Tensilica Xtensa LX Processor and HiFi 2 Audio Engine

Stretch licensed Tensilica’s Xtensa LX processor and HiFi 2 Audio Engine for use in their next-generation Software Configurable Processor. The Stretch S6000 family of processors is targeted towards audio/video applications and achieves unrivaled video processing performance using a dual issue, VLIW configuration of the Xtensa LX processor coupled with the second generation of Stretch’s Instruction Set Extension Fabric (ISEF).

Craig Lytle, Stretch President and CEO commented; “The ability to accelerate a target application for the Xtensa processor through the creation of Tensilica Instruction Extensions in real time, is key to achieving the breakthrough performance levels needed by today’s demanding audio/video processing applications. We are delighted to be extending our relationship with Tensilica into our new S6000 family and are tremendously excited about the performance levels we have been able to deliver in this platform.”

For more information, see http://www.tensilica.com/news_events/pr_2007_03_05.htm

New Energy Estimator Tool Guides Designers to Energy-Efficient SOC Architectures

To address the growing need to pro-actively reduce power consumption in embedded systems, Tensilica announced the Xenergy estimator, a unique energy estimator for both Xtensa configurable processors and Diamond Standard processors. By using the Xenergy tool to optimize for energy early in the SOC design cycle, designers can cut processor and local memory energy requirements by up to half by making intelligent design trade-offs.

“Xenergy will naturally appeal to designers of portable, battery-driven devices such as cellular phones and personal media players, but also to designers of complex SOCs in home entertainment and networking devices where heat is becoming a huge issue,” stated Chris Rowen, Tensilica’s president and CEO. “Tensilica is the first company to provide a realistic way to easily estimate the overall energy impact of different processor configurations and extensions together with application code tuning on each processor with its memory subsystem. The improvement in power at the architectural level is quite dramatic and productive, often dwarfing the power savings painfully achieved at the RTL and physical design levels.”

For more information, see http://www.tensilica.com/news_events/pr_2007_02_26.htm

Penstar Technology Licenses Diamond 330HiFi Audio Processor Core

Penstar Technology has licensed Tensilica’s Diamond Standard 330HiFi Audio Processor core for use in a new SOC design for cellular phones and personal media players (PMPs) conforming to China’s emerging Audio Video coding Standard (AVS). Penstar intends to be the first Chinese company to offer a low power chip that is fully compliant with AVS, following the successful release of its DS-1000 IC product, which is an AVS video decoder IC supporting both standard and high definition video applications for digital TV and IPTV (Internet Protocol TV). Penstar will use the Diamond Standard 330HiFi Audio Processor for both the audio and control functions in the SOC.

For more information, see http://www.tensilica.com/news_events/pr_2007_02_13.htm

Plato Networks Adopts Diamond 108Mini For Upcoming 10Gigabit PHY Design

Plato Networks has licensed the Diamond Standard 108Mini processor core for an upcoming 10 Gigabit Ethernet physical layer transceiver (PHY) chip design. Plato Networks is developing low-power, single-chip, 10 Gbps physical layer ICs for low-cost copper cabling based on the newly approved IEEE 10GBASE-T standard (802.3an).

“We needed the flexibility of a small 32-bit processor core for the evolving requirements of the 10 Gbps PHY market,” stated Pirooz Hojabri, vice president of engineering, Plato Networks. “The Diamond Standard 108Mini was the perfect fit from a size, power, code density, and cost perspective.”

For more information, see http://www.tensilica.com/news_events/pr_2007_02_12.htm

Tensilica to Showcase Mobile Phones Featuring Its Audio and Video Processors at 3GSM

Tensilica, Inc. will be showcasing mobile phones incorporating its audio and video processors at its booth at the 3GSM World Congress (Hall 2, Level 1, Booth 2.1A67) in Barcelona, Spain, February 12-15, 2007. Tensilica is the leading IP (intellectual property) supplier for mobile multimedia (audio and video) processor cores with its HiFi 2 Audio Engine, its Xtensa configurable processors, and its Diamond Standard VDO (video) family. Tensilica will showcase phones from Cingular, LG Electronics, Motorola, and Samsung that include Tensilica processor cores performing audio and video encoding and decoding.

For more information, see http://www.tensilica.com/news_events/pr_2007_02_07.htm

AM3D’s 3D Mobile Handset Audio Now Available for HiFi 2 Audio Engine

AM3D’s Zirene Audio Enhancement and Diesel Power MobileTM 3D Audio products are now available for Tensilica’s HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. Tensilica’s HiFi 2 Audio Engine with AM3D’s 3D audio will be demonstrated at the 3GSM Conference in Barcelona February 12-15 in Hall 2, Level 1, booths 2.1A67 (Tensilica) and 2.1B72 (AM3D).

“AM3D’s 3D audio products provide outstanding audio quality, 3D and special effects for mobile phones and portable music players,” stated Larry Przywara, Tensilica’s director of mobile multimedia products. “By adding AM3D’s audio software to our HiFi 2 product line, we can provide one programmable engine that runs all of the best-in-class audio software.”

For more information, see http://www.tensilica.com/news_events/pr_2007_02_06.htm

LG Electronics Licenses Tensilica’s Diamond Standard 330HiFi For High Quality Audio in Mobile TV Chipset

LG Electronics of Korea has licensed Tensilica’s Diamond Standard 330HiFi Audio Engine, the industry’s most popular audio processor core for cellular handsets. LG Electronics will use the Diamond Standard 330HiFi Audio Engine in next-generation mobile TV chipset designs.

LG Electronics currently uses Tensilica’s Xtensa processors for video and control processing in their Terrestrial Digital Multimedia Broadcasting (T-DMB) phone.

“We picked Tensilica’s Diamond Standard 330HiFi Audio Engine for three main reasons: low power, availability of a wide range of audio codecs, and our strong relationship with Tensilica’s technology in our DMB group,” stated Dr. Woo-Hyun Paik, Vice President of LG. “Tensilica’s Audio Engine is a proven solution, ready to drop into our next-generation designs.”

For more information, see http://www.tensilica.com/news_events/pr_2007_02_05_LG.htm

S2C Becomes Newest Tensilica Prototyping Partner in China

Tensilica announced a new SOC prototyping partnership with S2C Inc., a leading provider of innovative FPGA-based ESL (electronic system level) and SOC prototyping solutions with a rapidly growing presence in the China market. S2C has already deployed Tensilica’s Diamond Standard 108Mini processor core into its TAI Logic Module FPGA-based ESL platform, and is working on a reference design and demonstration platform for Tensilica’s popular Diamond Standard 330HiFi Audio core.

“S2C will be a valuable partner in helping us speed up the adoption of our Diamond Standard processors in China,” stated Steve Roddy, Tensilica’s vice president of marketing. “Customers will be able to rapidly evaluate and implement our processor cores into their SOC prototypes that can run at near-real time and real time speeds and accelerate hardware/software co-design.”

For more information, see http://www.tensilica.com/news_events/pr_2007_02_05_S2C.htm

Tensilica Licenses Xtensa LX2 Configurable Processor to Marvell

Marvell has taken a company-wide license to Tensilica’s Xtensa® LX2 configurable processor. This agreement was driven in part by Marvell’s successful use of Tensilica’s earlier Xtensa processors in high-volume printer applications, Yukon® gigabit Ethernet products, and LinkStreet® router products. Marvell plans to use the Xtensa LX2 configurable processor in various products throughout the company.

“By using Tensilica’s Xtensa processors in three very high-volume product lines, Marvell is able to take advantage of the extreme flexibility that these configurable processors provide for our design teams,” stated Alan Armstrong, vice president of marketing for Marvell’s Storage Business Group. “Our design teams will be able to deploy Tensilica processors in a broad range of roles, including many non-traditional design sockets within datapath and dataplane functions.”

For more information, see http://www.tensilica.com/news_events/pr_2007_02_01.htm

Tensilica Adds G.729AB Speech Codec for HiFi 2 Audio Engine

Tensilica introduced another codec for its popular HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core which are specifically optimized for audio in mobile multimedia devices. The G.729AB speech codec, mostly used in Voice over IP (VoIP) applications, is fully compliant with ITU (International Telecommunication Union) specifications for the G.729 standard with annexes A and B. As an ITU standard, G.729 is one of the most tested and lowest bandwidth digital speech transmission standards.

For more information, see http://www.tensilica.com/news_events/pr_2007_01_31.htm

Epson Licenses Xtensa LX for Printer Designs

Seiko Epson Corporation (“Epson”) has closed a long-term, multi-year license of Tensilica’s Xtensa family of configurable processor cores for Epson’s new REALOID printer engine chip. The first generation REALOID chip is used in Epson’s latest photo-capable inkjet printers and multi-function printers (MFPs), including the newly announced Colorio PM series MFPs. The Epson Stylus Photo R380 Ultra High-Definition REALOID-based printer is now available in the US. The strategic relationship also includes next-generation REALOID designs.

Epson’s engineers added Tensilica Instruction Extensions (TIE ) to customize several different Xtensa LX processors, each for a unique step in the inkjet image processing chain. By utilizing unique features of the Xtensa LX processor which allow direct high-speed data communication between the processors and thereby avoid the time delays of bus-based data traffic, Epson’s engineers were able to reduce the time required to print a single page to less than a third of that required by previous generation inkjet printers. These new printers can print borderless 4 x 6 photos as fast as the highest printing speed for black and white text.

For more information on this interesting application, see http://www.tensilica.com/news_events/pr_2007_01_30_Epson.htm

Sony Licenses Xtensa LX2

Sony Corporation has renewed and updated its license for Tensilica’s Xtensa LX2 configurable processor.

“Sony’s engineers realize the value of using a configurable processor to lower power and significantly improve performance in hand-held, battery powered devices,” stated Chris Rowen, Tensilica’s president and CEO. “We expect the Xtensa LX2 processor core will be used in designing Sony’s future consumer product and look forward to working with them on their next-generation design projects.”

CoWare’s Platform Architect Fully Supports Tensilica’s Configurable and Standard Processors

CoWare and Tensilica announced they have collaborated to deliver a comprehensive ESL design environment with CoWare’s Platform Architect for Tensilica’s processors. CoWare will distribute a SystemC-based Processor Support Package (PSP) with the flexibility to match all configurations of Tensilica’s Xtensa configurable processor family as well as Tensilica’s Diamond Standard family of processor cores.

Design engineers can now use CoWare’s Platform Architect ESL environment to do full architectural exploration, design verification, and software development when designing with Tensilica’s Diamond Standard processors and Tensilica’s highly-configurable Xtensa processors. This collaboration provides a huge productivity boost for SoC designers, as it not only speeds the design process, but also enables parallel development of the hardware and software.

For more information, see http://www.tensilica.com/news_events/pr_2007_01_23.htm

Tensilica Introduces TurboXim Fast Functional Simulator 40-80x Faster than ISS, Automatic SystemC Model Generation

Tensilica announced the new TurboXim fast functional simulator, which is 40 to 80 times faster than Tensilica’s proven cycle-accurate ISS (Instruction Set Simulator).

Tensilica also introduced its ability to automatically generate SystemC models to match all possible configurations of its Xtensa configurable processors and Diamond Standard series processors.

These introductions significantly speed ESL (embedded system level) design and architectural exploration for SOC (system-on-chip) design using one or more Xtensa configurable processors or Diamond Standard processors.

For more information, see http://www.tensilica.com/news_events/pr_2007_01_22.htm

CPU Cores and IP for Networking Seminar

On January 31, The Linley Group will host the first seminar of its Linley Tech 2007 series. This one-day event will focus on CPU cores and other licensable intellectual property (IP) and is intended for designers of ASICs and SoCs (systems on a chip). Leading IP vendors will explain how their technology can be used in networking and communications applications. Get the information you need to jumpstart your design!

The seminar will open with a presentation from The Linley Group highlighting recent trends in intellectual property. The program includes a session on CPU cores for ASICs and SOCs, featuring presentations on how to get the most out of popular ARM, MIPS, Power, and Tensilica CPUs. The event also includes a session on other IP for networking, including security, high-speed interfaces, and wireless technology. We have an outstanding lineup of speakers and talks, including:

Sumit Gupta, a product marketing manager at Tensilica, will present "Networking Applications for Xtensa Configurable CPU Cores."

This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Register now to guarantee your place. The seminar is targeted at ASIC and SoC designers, OEMs, press, and the financial community. Your free attendance is made possible by our event sponsors: Freescale, Tensilica, SafeNet, MIPS, Rambus, IBM, and ARM. Sign up now at: http://www.linleygroup.com/seminars.html

Virage Logic - Tensilica Net Seminar

Optimize Area, Performance or Power with Tensilica and Virage Logic Core-Optimized IP Kits
January 24, 2007 - 11 am PST/2 pm EST - Register Now!

Join Virage Logic and Tensilica for an informative technical webinar on the recently introduced Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family. Specifically tuned to optimize the performance of Tensilica's Diamond Standard product line processor cores, this joint collaboration provides mutual customers with physical IP that leverages Virage Logic's silicon proven embedded memory IP and standard cell libraries to meet a variety of market requirements. The Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores on TSMC’s 130-nanometer (nm) and 90nm G processes.

Learn how customers can utilize easy instant access to a series of jointly-developed Core-Optimized IP Kits specifically optimized for each of the Diamond cores that allows designers to target area, performance or power for a greater competitive advantage.

You won't want to miss this exclusive technical webinar where Virage Logic and Tensilica will jointly provide an overview of the Core-Optimized IP Kits and then show how Virage Logic's highly differentiated, silicon proven semiconductor IP has been optimized specifically to enhance Tensilica’s Diamond Standard processor cores.

Tensilica’s Diamond Standard Processors Receive Prestigious Portable Design Editor's Choice Award

Portable Design Magazine named Tensilica's Diamond Standard Processor family as a recipient of its prestigious Editor's Choice Award for 2006. Only 11 products were picked for this award for 2006.

According to Portable Design, “Every year Portable Design reviews several hundred products intended to make life easier for designers of portable electronic devices... We recognize the best of the best with our 2006 Editor's Choice Award. We believe that these products are indicative of the creativity our readers bring to bear, and they're worthy of the wider recognition that this award will bring."

See Portable Design's Editor's Choice award recipients.

Tensilica Mourns Friend and Board Member, Richard Newton

Tensilica mourns the death of our friend and board member Richard Newton. Rich's energetic presence will be missed by us all. We extend our sympathies to his family and friends. (EETimes story on his passing)