Tensilica In Set-Top Boxes

Tensilica's HiFi 2 Audio Engine is now designed into set-top boxes. See the news about the latest design win for Intel's CE4100 media processor. According to the press release, "This new generation of Amino products will address growing consumer demand for TV-based entertainment from any source - including broadcast, on-demand and open Internet “Over-the-Top” (OTT) services. Using the new Intel® Atom™ Processor CE4100 will enable Amino to develop new types of hybrid/OTT devices that offer unparalleled flexibility and functionality."

Have a Wonderful Christmas

As I'm sitting here on the last working day before Xmas, I'm so happy to be working here at Tensilica and blogging away. There's so much happening that I almost can write an entry every day. I'll be back at work the week between Xmas and New Years, getting ready for CES and other things happening next year.

What's Hot at CES? See what BusinessWeek and GigaOm Think

Look at Android-Driven Home Entertainment. MIPS Technologies and Tensilica just announced a joint system-on-a-chip alliance that's designed to accelerate the deployment of the open-source Android operating system in home entertainment devices. (MIPS already has its own Android distribution focused on the same goals.) At CES the companies will be demonstrating the potential of their joint alliance for everything from Android-based "mobile wireless phones to low-cost digital picture frames, high-definition DTVs, set-top boxes, Blu-ray disc players, and more," as they note in their announcement.

ConnX D2 DSP Wins EDN's Top 100 Products of 2009 Award

Only 4 DSPs were cited as the top electronic products of 2009 - and the ConnX D2 was one of them! The ConnX D2 DSP engine delivers outstanding 16-bit fixed point "out of the box" performance on compiled C code, without the need for assembly code optimization. This allows SOC development teams to have greater flexibility in resource allocation as well as the ability to quickly change algorithms. C code optimized with TI C6x or ITU C intrinsic functions compiles directly to the ConnX D2 instruction set, allowing developers to benefit from pre-existing TI and ITU code bases.

MIPS and Tensilica - Together on Android

A joint demo of a MIPS32 processor core integrated with Tensilica's HiFi 2 Audio DSP will be on display in suites that both companies have at the Consumer Electronics Show in Las Vegas, January 7-10, 2010. Together, MIPS and Tensilica will help companies speed the design of new home entertainment and mobile consumer products based on Android.

Xmas gift idea: Denon DVD players

The Denon 2930CI, 3930CI and 5910CI Progressive Scan DVD Audio/Video/Super Audio CD Players use Silicon Optix's Reon-VX HQV processing to deliver very high picture and sound quality. The DVD-5910CI uses the finest 10-bit I/P converter, capable of performing one trillion operations per second, to not only dramatically improve motion detection but also accurately detect and correct lines on a per-pixel basis to effectively avoid "jaggies."

CoWare and Tensilica Deliver Software Development Solution for Multi-Core Tensilica-based Platforms

Coware and Tensilica are collaborating to further enhance the integration of Tensilica's processor models into the CoWare tools to support CoWare's advanced functionality to ease software development on multi-core Tensilica-based SOC designs. The enhanced solution is being used by joint CoWare-Tensilica customers in automotive, consumer and wireless markets.

Xmas gift idea: Nitendo DSi game

A Tensilica processor handles the control functions in the WiFi chip inside each Nitendo DSi game.

Xmas List: AMD ATI Graphics Boards

Get the really good ones with the UVD, a dedicated video decode processing unit. UVD-powered AMD ATI graphics chips include the HD4000 series, the HD3000 series, the HD2000 series, the x1900 series, the x1600 series, and the x1300 series.

Xmas List: HD Radio for your iPhone

Today's gift idea is a simple dongle that adds HD radio to your iPhone - $80 exclusively at Radio Shack, it features Tensilica inside. SEe http://www.insideradio.com/Article.asp?id=1580560&spid=32060 for a review.

Xmas List: HP LaserJet Printers

Priced from $100-$150, the HP LaserJet P1005 and P1006 small-form-factor printers are the ideal gift. What a workhorse (I have one at home). Tensilica inside!

Tensilica Delivers New Design Flow Support for Synopsys’ Galaxy Implementation Platform Technologies

We now provides out-of-the-box automated design flow support for key technologies within Synopsys' Galaxy Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica's new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15% improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows, thus offering immediate benefits to Tensilica customers.

Top EDA Companies Endorse Tensilica’s Pin-Level SystemC Models

Cadence, Mentor and Synopsys endorse Tensilica's pin-level SystemC models. The pin-level models are a natural extension of Tensilica's pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC), and allow designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators, and do not require the usage of any specialized hardware/software co-simulation tool.

Enhanced Tools for Dataplane Processor Design and Software Development

Our eighth generation tools further automate customized Xtensa dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE), and pin-level co-simulation with RTL. These enhancements further strengthen Tensilica's leading position as the highest performance, and most complete, customizable processor core solution for SOC designs.

Microprocessor Report Reviews Xtensa LX3 and Xtensa 8 Processors

See why they conclude: "The Xtensa LX3 establishes a solid foundation for Tensilica’s
data-plane strategy and builds on the stellar performance of the Xtensa LX2. The new features and options will offer developers more flexibility to create optimized designs."

545CK - the Fastest DSP Core

What makes the 545CK so fast according to industry benchmarks? It's a 3-issue VLIW DSP with 8-way SIMD units and an extremely efficient compiler that automatically vectorizes code. If you need a fast DSP, this is the one for you. Or you can create a DSP of your very own to match your application.

Whitepaper: Using Processors in the SOC Dataplane

Now for your after Thanksgiving reading pleasure - find out how you can use processors in the SOC dataplane (they're not just for control any more) - by connecting processors directly to RTL - avoiding the bus and getting high-speed data throughput.

Happy Thanksgiving Week everyone

It's a good time to be thankful for all of the interesting people who work in technology - they make my life very interesting and are responsible for such great innovative products. Happy Thanksgiving everyone. We'll be closed in the US on Thursday and Friday.

Samsung Signs for HIFi 2 for Home Entertainment Products

The Digital Media & Communications Business of Samsung Electronics has signed a multi-year license to Tensilica's HiFi 2 Audio DSPfor use in Samsung's multimedia system products after a successful previous deployment in Samsung's System LSI Division. Tensilica's HiFi architecture is the most popular commercial audio core for system-on-chip designs.

"We selected the Tensilica HiFi Audio DSP because of its impressive performance capabilities and because of the breadth of software codecs available," stated K.W. Chun, vice president, Digital Media & Communications Business of Samsung Electronics. "The HiFi 2 Audio DSP can execute the most demanding multi-channel audio algorithms at remarkably low MHz and low power."

How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors

HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.

White paper on Blu-ray Audio

Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.

"Trends in Heterogeneous Multicore SoCs" by Grant Martin

Restructuring the problems once reserved for General-Purpose Processors (GPPs) into application-specific units creates interesting options for designers. Grant discusses the architecture for Application-Specific Instruction set Processors (ASIPs) matched to dataplane tasks and more. See http://www.embedded-computing.com/articles/id/?4304

New IEEE Computer Article features Work at Lawrence Berkely Labs

See the article in the Nov. issue of Computer titled "Energy-Efficient Computing for Extreme-Scale Science" by CTO Chris Rowen and others about the work on low-power design at Lawrence Berkeley Labs. http://www.tensilica.com/uploads/pdf/ieee_computer_nov09.pdf

Everything You Know about Microprocessors is Wrong

Here's a great web seminar that's archived, so you can view it any time. Many system-engineering concepts and "best practices" with respect to system design are no longer valid at the chip level. For example, bus-centric design--made popular by the introduction of the first commercial microprocessor in 1971--continues to dominate on-chip design 36 years later even though nanometer silicon has completely changed the rules of system interconnect.

Xtensa 8 and LX3 are out - it's time to party

Today we have a company-wide bowling tournament offsite to celebrate the release of our eight generation processors - Xtensa 8 and Xtensa LX3. Fun for all!

What's the fastest route from C algorithm to gates?

You've got an algorithm written in C. You can quickly see how that will run on a standard processor core, but you'd be amazed how much faster that algorithm can run on a specially tailored processor. A simple example is an audio stream. If the datapath of a processor is specially tailored just for audio data, that's going to go through the processor much faster, and therefore better quality sound. The same holds true for other data-intensive applications, especially when the datapath doesn't exactly fit into 32 bit words. Find out more from this white paper: http://www.tensilica.com/products/literature-docs/white-papers/fast-path-from-c-to-gates/

Xtensa 8 or Xtensa LX3?

Xtensa LX3 is a superset of Xtensa 8 and adds some very powerful features. Find out more at http://www.tensilica.com/products/xtensa-customizable/xtensa_choice.htm

Grant Martin at Synopsys Interoperabity Forum Tomorrow 1:15 in Santa Clara

See our Chief Scientist talk in the System-level design section - topic: Getting high with a little help from my friends: Configurable processor interoperability with ESL tools.

Xtensa LX3 - 10 GigaMAC/Sec DSP Performance, tops 1 GHz

The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.037 mm² and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm² (post place-and-route 45GS) and consuming just 170 mW (including leakage).

Grant Martin in Tutorial at ICCAD 4:30 today

Embedded Processors, Methods and Applications: Computer Architects Perspective

As feature sizes diminish and transistors multiply, designers are compelled to move to higher levels of abstraction to overcome the productivity gap. Increasingly designers use processors as the main module in embedded system design. The available choices to the modern designer include processor (which are both non-configurable and configurable), DSP and GPU cores. This tutorial explores the available processors, details methodologies and explains applications.

The tutorial is divided into three parts: the first will explore the field of embedded processors; the second will look design methodologies based on embedded processors; the third, will describe an application in detail. This tutorial will be presented by three experienced researchers with industrial and academic experience, and will benefit students, researchers, and design engineers.

Speakers:

Grant Martin - Tensilica, Inc.
Sri Parameswaran - Univ. of New South Wales
Anand Raghunathan - Purdue Univ.
http://www.iccad.com/events/eventdetails.aspx?id=106-3-E

Sign up for our Web Seminar: The 5 Pitfalls of 4G Baseband Design

Sign up now for our web seminar next Tuesday, October 27, at 11 am pacific daily time. It will be recorded, so you can watch it later, too. Chris Rowen, our CTO, will talk about the emerging LTE standard, which is complex, requires extraordinary computation throughput and much better power efficiency than previous wireless baseband PHY subsystems. Because of the complexity, designers are taking many different approaches to chip design for LTE.

This webinar explores five significant challenges faced by designers of efficient digital basebands, including pitfalls in LTE's many modes, excessive cost and power, the "million MIPS" hurdle of Turbo decoding, and the dilemma of choosing the right communications among the LTE building blocks. This webinar uses detailed examples from an end-to-end LTE PHY baseband architecture to highlight the key dos and don'ts. http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=tensilica_oct2709

More Configuration Optons Than Ever in Xtensa 8

Want your processor core your way but don't want to work hard at it? Just look at all of the configuration options you get with Xtensa 8. Just click on a button or use a pull-down menu to make your selections - then you can get your processor you way. See http://www.tensilica.com/products/xtensa-customizable/xtensa/configurability.htm

Xtensa 8 - Our 8th Generation Processor with Novel I/O

By embedding functionality right into the processor datapath itself, designers can use the Xtensa 8 DPU to not only perform control functions, but also some of the finite state machine tasks that manage RTL blocks and some of the RTL functionality as well. This makes for a smaller, more efficient chip design, and it significantly reduces the verification challenges associated with new RTL designs. See http://www.tensilica.com/products/xtensa-customizable/xtensa.htm

Monday's Big News - Stay Tuned!

Busy today putting the finishing touches on the website update for a new processor announcement on Monday. Very cool stuff.

Why use Tata's Ro-SES OS?

Today we announced that Tata Elxsi's RoS-ES (Real Time Operating System for Embedded Systems) OS is now available for Xtensa and Diamond Standard processors. So why use a small OS like this rather than Linux? When you're using deeply embedded controllers in the dataplane, you don't need all the overhead of most OSes. Tata Elxsi's RoS-ES is a compact real-time operating system (RTOS) that provides an impressive array of capabilities making it well suited to networking and consumer electronics applications. More information on the RoS-ES RTOS is available at www.tataelxsi.com/roses.

Multiple Codec Operation Apnote

This application note describes a multi-stream audio decoder test bench that works without needing a threading operating system. A software test bench is provided for the Diamond 330HiFi processor that supports decoding and audio mixing of an arbitrary number of homogenous or heterogeneous audio streams. This application note describes the test bench, and discusses the coding techniques used to reduce memory requirements and to synchronize/mix audio decoded from multiple streams.
http://www.tensilica.com/products/literature-docs/application-notes/audio-application-notes/multiple-audio-codec.htm

Hi Fi Audio DSP Gets DTS-HD Master Audio Certification

Tensilica's HiFi Audio DSP is the first IP core to achieve certification. Having the HiFi DSP IP core certified independent of the choice of silicon implementation will significantly ease Tensilica's customers' efforts to design Blu-ray Disc and Audio Video Receiver SOCs and complete chip and system level certification with DTS.

White Paper: Get Your ASICs Off the Bus

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.
http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/

Interesting apnote on Optimizing for Low Power

It's amazing how little decisions can make a big difference in energy consumption. Read our apnote: Optimizing for Energy using the Xenergy Energy Optimizator Tool.
http://www.tensilica.com/products/literature-docs/application-notes/xtensa-tools/xenergy-energy-optimizator.htm

Whitepaper: How to Manage Video Frame-Processing Time Deviations

Whitepaper: How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors - you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after. http://www.tensilica.com/products/literature-docs/white-papers/video-frame-processing/

CTO Chris Rowen Giving Baseband Talk Tomorrow at SOC Conf in Tampere

From 13.20-14.40 Rowen will discuss A DSP architecture optimized for wireless baseband. The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations. http://soc.cs.tut.fi/2009/Technical_program.php

White Paper: TIE - The Fast Path to High Performance Embedded SOC Processing

TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power. http://www.tensilica.com/products/literature-docs/white-papers/tie---the-fast-path.htm

Excellent AMD ATI Video with Xtensa

Tensilica's processors configured to accelerate video stream decoding are an ingredient in every UVD-powered AMD ATI graphics chip, including those iwth ATI Avivo HD video and dipslay techology, which provdes PC users with crisp images, smooth videos and true-to-life colors. UVD is a dedicated video decode processing unit introduced with the ATI Radeon HD 2000 series graphics processors that offloads the CPU from the decoding process. UVD technology reduces power use, helps decrease system noise and helps to increase notebook battery life during HD video playback. AMD's graphics products provide for DirectX10 gaming and allow PCs to be hooked up to big-screen TVs with HDMI and built-in 5.1 surround sound audio to enjoy Blu-ray and HD DVD movies. http://www.tensilica.com/markets/customer-gallery/graphics.htm

Everything You Wanted to Know About Blu-ray Audio

Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.
http://tinyurl.com/yc9ekeq

The Fastest DSP Core Tested by BDTI

See BDTI's report on Xtensa LX - the fastest DSP core BDTI has ever tested. http://www.tensilica.com/uploads/pdf/BDTI-tensilica_wp-1.pdf

Apnote: Fast Interrupt Handling

Fast interrupt handling is important to system throughput and responsiveness. This application note describes a method to use existing Xtensa features and configuration options to support very fast interrupt handling. This note focuses on the interrupt handling case, i.e, that case where one task is running, but is preempted at some random point by an external or timer interrupt, which then performs an independent task. See http://www.tensilica.com/products/literature-docs/application-notes/system-software/interrupt-handling.htm

White Paper: Get Your ASICs and SOCs Off the Bus!

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.

http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/

Whitepaper: 10 Tips for Successful SOC Design

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design. See http://www.tensilica.com/products/literature-docs/white-papers/10-tips-for-soc-design/

2pm PT today (Wed) - See Grant Martin at SOC Online Conference

EETimes SOC online conference today - see 2pm discussion: Economics of Next-Generation SoC Design: A node too far? with Tensilica Chief Scientist Grant Martin. More info at http://tinyurl.com/lrhr6l Don't miss it!

Have You Checked the Processor and DSP Checklist?

SOC designs are major, high-risk projects and most consist of many IP blocks-some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and EDA flow scripts, these processor IP blocks can literally make or break your project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. http://www.tensilica.com/products/literature-docs/white-papers/ia-processor-dsp-ia-processor-and-dsp-iip-selection-checklist.htm

New ConnX Baseband Engine Product Brief

See what a DSP with 16 18-bit MACs/cycle can do for you. Perfect for next-gen baseband radios and receivers. Hot off the press (or at least newly posted to the web site). http://www.tensilica.com/uploads/pdf/connx_bbe.pdf

Sign Up Now For EETimes SOC Online Conference Wed 9/16

Tensilica's Chief Scientist Grant Martin will participate in panel at 5 pm Eastern Time: Economics of Next-Generation SoC Design: A node too far?

The cost of both design and manufacturing is growing exponentially at each new technology node. The largest chip companies will continue to push scaling forward for the foreseeable future. But what about the rest of the field? At what point does it stop making sense for companies to move to the next node? To what degree is this a function of design and/or verification costs? In what application areas does it make sense for companies to deploy FPGA-based SoC designs. This panel will examine the state of the economics of different forms of SoC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon.

See the entire schedule and sign up now: http://www.eetimes.com/soc/program_schedule/;jsessionid=1UQ1JNW4L3TCPQE1GHPSKH4ATMY32JVN

It's what they don't tell you about power specs that matter.

Anyone familiar with board-level design has developed an intuitive feel for packaged-processor power specifications: the processor draws a certain amount of power, give or take a percentage based on process variation and speed binning. For a variety of reasons, this intuition utterly fails with respect to vendor specifications for processor core IP. Read our white paper: Processor Core Power Specs: A Cautionary Tale at http://www.tensilica.com/products/literature-docs/white-papers/power-specs/

Have You Seen the Video?

See how easy it is to configure an Xtensa processor with just the options you need. Tensilica's CTO Chris Rowen leads you through an actual example. http://www.tensilica.com/products/xtensa-customizable/configurable.htm

Read Microprocessor Report's review of ConnX Baseband Engine

Every "radio" in notebooks, netbooks, smartphones, mobile Internet devices, WiMAX, DTV, digital radio and more - with a chip-scale wireless transmit/receive unit - needs a baseband processor. See what Microprocess Report had to say about Tensilica's Baseband Engine. http://www.tensilica.com/uploads/pdf/MR_baseband_0809.pdf

Back from vacation - now back to work

Just spent a very nice week in South Lake Tahoe - we're so lucky in California to have wonderful places to drive to for vacation. Now I'm back and getting into the swing of things here at Tensilica. We're going to have a busy fall.

Tata Elxsi's DSP SW Runs on ConnX D2 DSP

Tensilica has tested optimized C source code from Tata Elxsi's extensive DSP software library and the existing code - including code optimized with industry standard C intrinsics - ran flawlessly on Tensilica's new ConnX D2 DSP engine. This means that designers can rely on Tata Elxsi's proven software services to quickly get new ConnX D2-based SOCs designed into innovative new products. This also means that other C code with intrinsics should work just fine on the ConnX D2 DSP.

New White Paper: Cut DSP Development Time

The magic is in the compiler technology. Learn how an advanced compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code. http://www.tensilica.com/products/literature-docs/white-papers/Cut-DSP-Development-Time.htm

ConnX D2 DSP Engine Combines Outstanding Performance, Compact Size, and Easy Programmability

New today - the high-performance, small, low-power ConnX D2 16-bit dual-MAC DSP engine for SOC designs. The ConnX D2 DSP engine provides uncompromised performance from C code, unlike many other DSPs that require time consuming assembly coding for maximum performance. This means that virtually any C program, including those written with C intrinsic functions for the TI C6x family or ITU (International Telecommunications Union) reference code, can run unmodified and with excellent performance on the ConnX D2 DSP engine. Find out more at http://www.tensilica.com/news/296/330/Tensilica-s-ConnX-D2-DSP-Engine-Combines-Outstanding-Performance-Compact-Size-and-Easy-Programmability.htm

Apnote: Multiple Audio Codec Operation

This application note describes a multi-stream audio decoder test bench that works without needing a threading operating system. A software test bench is provided for the Diamond 330HiFi processor that supports decoding and audio mixing of an arbitrary number of homogenous or heterogeneous audio streams. This application note describes the test bench, and discusses the coding techniques used to reduce memory requirements and to synchronize/mix audio decoded from multiple streams.
http://www.tensilica.com/products/literature-docs/application-notes/audio-application-notes/multiple-audio-codec.htm

New Ap Note on TIE Ports

Why do so many designers pick Tensilica's Xtensa LX? TIE Ports are an important part of the answer. They let you bypass the bus and connect directly, much like GPIO. Read this application note and find out how you can significantly increase I/O speed, unlike any other processor core.

Microprocessor Report Reviews ConnX Baseband Engine

See the 9-page in-depth review of Tensilica's new ConnX Baseband Engine written by Tom Halfill of Microprocessor Report (http://www.mdronline.com/mpr/index.html). If you are not a subscriber, email paula@tensilica.com for your free pdf of this important review.

White Paper on Digital Audio

Whitepaper: Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

Digital audio has rocketed to the top of the critical features list for all sorts of products over the past several years. At the same time, the number of digital audio codecs and audio-enhancement programs has exploded. Now most consumer products must support multiple codecs and offer a broad range of audio-enhancement features.

This has created high demand for a flexible, high-performance, low-power audio engine that adds sound to an SOC's design with the least amount of design effort and a small on-chip footprint. Tensilica's HiFi 2 Audio Engine was carefully crafted to meet the requirements for the broadest possible range of consumer products, from mobile music players to in-home high-end entertainment centers. Read the white paper:
http://tinyurl.com/nop5bl

Ap note: Implementing the Advanced Encryption Standard on Xtensa Processors

This application note examines the Advanced Encryption Standard (AES) cipher and illustrates the power of a configurable processor in accelerating encryption and decryption. Xtensa-based application-specific processors are quickly designed, simulated, and instantiated in silicon. These processors offer performance that rivals hardware solutions along with the benefits of flexibility, programmability, and ease of verification found with purely software implementations. The processor extensions proposed in this application note give the Xtensa processor a speedup of over 300x compared to a base Xtensa processor or a similar 32-bit RISC engine such as ARM9, MIPS32, etc. See http://www.tensilica.com/products/literature-docs/application-notes/tie-application-notes/advanced-encryption-standard.htm

Tensilica Great Race Results

Tensilica great race results: First place: Brian Withers. Second place: Jack Guedj. Third place: Stuart Fiske - the prize? A bottle of Champaigne - the drink of champions

Tensilica's "Great Race" today

This afternoon at 3 employees will meet for Tensilica's "Great Race". Walkers and runners will be entered into a raffle for a grand prize. Wonder what it is?

Design Automation Conference (DAC) wrap-up

I went up to San Francisco yesterday (Tuesday) to attend DAC. I heard it was much busier on "free" Monday. It was pretty quiet yesterday, but that's because a lot of the good activity is happening in vendor suites or in the technical sessions. That leaves little time to wander the halls. Many booths were just front-ends to the suites, where the action was happening as vendors gave demos of new tools and capabilities. People with little companies with small booths and no suites looked like they were getting pretty bored with the lack of hall traffic. There were very few flashy booths - the XJTAG girls in their short skirts were about as exciting as it got. Why don't they just let qualified people in for free every day? The more traffic, the better the show.

Synopsys and Cadence issued press releases about their efforts to create workable tools for 32 nm designs - let's hope they can really make their tools work. The show is still going on today at Moscone center.

Virtutech Now Supports Xtensa Cores

Need to create a virtual mixed-architecture SOC? Try using Virtutech's Simics, which allows engineers to adopt a virtualized systems development approach, resulting in faster product definition, development and deployment in comparison to traditional hardware centric approaches. It supports over 40 cores! See the press release at http://www.tensilica.com/news/294/330/Virtutech-Simics-Processor-Support-Grows-to-Include-Multicore-RMI-XLR-MIPS64-and-Configurable-Tensilica-Xtensa-Cores.htm

Validity Sensors Licenses Two Tensilica Processors for High-Volume Fingerprint Sensors

"Power, performance and die size are critical factors in our leading edge sensor designs," stated Alex Erhart, EVP of products at Validity Sensors. "Moving up from a 16-bit controller to a 32-bit controller creates a lot of opportunities to add enhanced features that need to be balanced with the area and power impact of a higher end controller. Tensilica's processors give us the speed we need with the lowest power and minimal die size. We were particularly impressed with the ability to customize the processors for our exact application requirements."

For more, see http://www.tensilica.com/news/293/330/Validity-Sensors-Licenses-Two-Tensilica-Processors-for-High-Volume-Fingerprint-Sensors.htm

New SW Design Center Supports Audio/Video and Security Apps

Calsoft is Tensilica's newest software design center. "We joined Tensilica's partner program because we have seen increasing interest in Tensilica's customizable processors among designers of next-generation video and audio chips," Sanjay Dube, Calsoft's director of business development. "As we combine our expertise in embedded technologies with skills in audio-video codec development and security applications, we are able to offer a unique set of services, including developing audio-video codecs, porting VoIP stacks, board support packages, software integration, protocols testing and QA. Now, equipped with Tensilica's full tool set, we can help companies with a variety of complex and diverse software requirements."

http://tinyurl.com/create.php

Blue Wonder Communications Uses Tensilica for LTE

"New design approaches are needed to successfully implement the LTE and LTE Advanced standards," stated Dr. Peter Meyer, managing director and head of development at Blue Wonder Communications. "The traditional approach of using hardwired logic for the performance-intensive PHY layer datapath simply won't work. Because LTE systems run at such high data rates, it would require millions of gates of logic developed with RTL (register transfer level) methods - and that creates a huge verification hurdle. Using Tensilica's automated processor creation tools we are able to quickly generate customized DPUs delivering the performance levels of custom hardware with the programmability of a processor."

See the press release at http://www.tensilica.com/news/291/330/Blue-Wonder-Communications-to-Develop-LTE-Baseband-IP-Using-Multiple-Optimized-Tensilica-Dataplane-Processors.htm

A Processor and DSP IP Checklist

"A Processor and DSP IP Selection Checklist" - This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle. http://www.tensilica.com/products/literature-docs/white-papers/ia-processor-dsp-ia-processor-and-dsp-iip-selection-checklist.htm

New white paper: 10 Tips for Successful SOC Design

One way to ensure SOC design success is to start out in the right direction. That's the purpose of this White Paper-to help you start out in the right direction. These ten SOC design tips come straight from the hard-won experience we have gotten from working with our customers on many types of SOC design projects for wireless, multimedia, communications, networking, computing, and storage applications.

http://www.tensilica.com/products/literature-docs/white-papers/10-tips-for-soc-design/

See How Easy it is to Configure a Processor

Yes, you can do this! Watch the video. Chris Rowen, our CTO, shows just how easy it is to pick the configuration options you need for your processor core: http://www.tensilica.com/products/xtensa-customizable/configurable.htm

See how Epson Uses Multiple Xtensa Processors in Printers

What's the secret behind Epson's Realoid chip inside their inkjet printers? It's not a secret any more. Find out how multiple Xtensa processor cores give more flexibility and programmability over previous generation hardwired RTL solution
http://www.tensilica.com/products/literature-docs/success-stories/epson-printers.htm

The ConnX 545Ck - the fastest DSP core ever

See why BDTI benchmarked the ConnX 545Ck as the fastest DSP core they've ever tested. See http://www.tensilica.com/products/dsps/545ck-new.htm

Accelerated Interrupt Handling Ap Note

Fast interrupt handling is important to system throughput and responsiveness. This application note describes a method to use existing Xtensa features and configuration options to support very fast interrupt handling. This note focuses on the interrupt handling case, i.e, that case where one task is running, but is preempted at some random point by an external or timer interrupt, which then performs an independent task.
http://tinyurl.com/ku4uwz

New White Paper on DSP

New white paper: Optimizing a DSP Architecture for Wireless Baseband. See http://tinyurl.com/ll25y8

New ConnX DSP Family

Tensilica today introduced a new family of high-performance DSPs IP cores - the ConnX DSP family - that include standard cores, click-box configurable options or a starting point for customized Xtensa LX DPUs for SOC designs.

"With its configurable instruction set, Tensilica has morphed its basic Xtensa RISC architecture to become a compelling DSP engine," stated Will Strauss, president of Forward Concepts. "The company's first giant leap into the DSP world was through the design of their HiFi 2 Audio Engine into cellular phones, Blu-ray Disc players, and other home entertainment products, where they've had considerable success. Now, with the ConnX DSP Baseband Engine, Tensilica is taking aim at the fastest growing part of the market - next generation wireless. They already have major customers - including Fujitsu, Panasonic and NEC - doing their own designs in this market. I expect they will do quite well with this high-performance DSP engine."

http://www.tensilica.com/news/290/330/Tensilica-Announces-New-High-Performance-ConnX-DSP-Family-for-LTE-and-4G-SOC-Designs.htm

Tensilica Introduces New ConnX Baseband Engine

The ConnX Baseband Engine enables efficient baseband processing for 3G, LTE (Long-Term Evolution) and 4G wireless equipment with its scalable, high-performance DSP architecture that provides industry leading computational throughput of 16 18-bit MACs per cycle. The ConnX Baseband Engine features an optimized instruction set, high memory bandwidth, scalable clustering, and efficient compiler support with an easy programming model for SIMD (Single Instruction, Multiple Data) vectorization and other DSP functions. This high performance core is also an effective solution for multi-standard fixed and mobile DTV broadcast demodulators.

http://www.tensilica.com/news/289/330/Tensilica-Announces-High-Performance-ConnX-Baseband-Engine-for-LTE-and-4G-Wireless-DSP-Handsets-and-Base-Stations.htm

DOCOMO Capital invests in Tensilica

DOCOMO Capital is the corporate venture arm of NTT DOCOMO, Japan’s leading wireless carrier.

“We recognize the growing importance of Tensilica’s customizable DPUs for semiconductors that enable lower power and innovative mobile devices, and that’s why we made this investment,” stated Tomoya Hemmi, president and CEO, DOCOMO Capital. “Tensilica’s high-performance DPUs for audio, video and baseband functions will be key enablers for new capabilities and increased battery life in future mobile telephones.”

For more information, see http://www.tensilica.com/news/288/330/Tensilica-Announces-Strategic-Investment-by-DOCOMO-Capital.htm

Try Trace-X for Free

Tensilica partner Xpress Logic offers free trial of Trace-X http://www.rtos.com/tracex/RequestDownload.php?source=webpage

See how easy it is to configure a processor

Watch Chris Rowen, Tensilica's CTO, configure a processor. See how easy it is to make the trade-offs you need. http://tinyurl.com/ltuvo3

Why use Tensilica cores for control tasks?

While they excel as dataplane processors, Tensilica’s Diamond Standard and Xtensa processors are ideal control processors and can be used as-is or tailored to match your performance targets. Tensilica's cores can be used as compact controllers, medium-performance RISC controllers, and high-performance RISC CPUs. See more at http://www.tensilica.com/markets/control-processor.htm

AES Ap Note

Application note: Implementing the Advanced Encryption Standard on Xtensa Processors - http://tinyurl.com/ltyhc2 - This application note examines the Advanced Encryption Standard (AES) cipher and illustrates the power of a configurable processor in accelerating encryption and decryption. Xtensa-based application-specific processors are quickly designed, simulated, and instantiated in silicon.

Just Launched New Web Site

We just launched a new web site for Tensilica. Come look around. You'll see videos, lots of app notes and documentation, and other good stuff.

EETimes article on Great Semi Company Gaffes

Just read this great article in EEtimes on the biggest recent mistakes by semiconductor companies: http://tinyurl.com/mzvamr

TranSwitch Integrates Tensilica Xtensa Processors into its Atlanta 2000 Gigabit-rate Communications Processor

TranSwitch Corporation has integrated two Xtensa customizable Dataplane Processor Units (DPUs) into its recently introduced Atlanta 2000 gigabit-rate communications processor product family.

Atlanta 2000 highlights the versatility of Tensilica’s DPUs. Although Tensilica is best known for its dominant position for the SOC (system-on-chip) dataplane applications, the Atlanta 2000 is an example of how Tensilica’s customizable DPUs can also be utilized as cores for the most demanding embedded CPU applications.

Diamond 106Micro Available Free Through Synplicity's ReadyIP Program

Did you know you could add Tensilica's Diamond 106micro 32-bit controller to your FPGA design - directly from your Syplicity Synplify Pro or Premier tools - for free? Yes, we want you to get to know how good Tensilica's processor cores are by trying out our smallest and most efficient core. See http://www.synplicity.com/partners/readyip/partners.html

Timesys offers LinuxLink for Tensilica Processors

With a LinuxLink subscription for your Tensilica Diamond core 232L processor, you will be able to:
- Quickly assemble and boot an initial embedded Linux image on your Tensilica 232L reference board board.
- Patch/configure/rebuild/update on your desktop with a properly installed and configured development environment.
- Debug/profile/tune with common open source development tools, including required kernel patches and development libraries/utilities.
- Obtain help on common development tasks with technical assistance and a rich library of Timesys-authored “How To” documentation.

https://linuxlink.timesys.com/3/Linux/Tensilica

SiliconXpress Becomes Newest Tensilica Design Center

SiliconXpress is a fabless chip provider, headquartered in Lubbock, Texas, offering one-stop design, fabrication, test, and packaging services.
See http://www.tensilica.com/news_events/pr_2009_05_26.htm

More on Nitendo DSi Game

Yes, we're inside, but not in the Bluetooth as previously written. We're inside the WiFi. Sorry about that.

Tensilica's Inside Nitendo DSi Game

Inside every new Nitendo DSi game, there's a Tensilica processor in the Bluetooth chip. Buy Tensilica and have a great time.

Follow Tensilica on Twitter

For instant updates, follow http://www.twitter.com/tensilica

Fastest Growing Semiconductor IP Company

Gartner named Tensilica the fastest growing semiconductor IP company for 2008.

Tensilica HiFi 2 Audio DSP Supports HE AAC by Dolby in Digital Radio Mondiale

The Digital Radio Mondiale (DRM) decoder is now available for our popular HiFi 2 Audio DSP. The implementation is based on software developed by Dolby and has passed Dolby’s certification procedure. Now designers of digital radio systems can use one processor core – Tensilica’s HiFi 2 Audio DSP – to run all decoders required throughout the world for digital radio, enabling a universal worldwide digital radio receiver. Tensilica’s HiFi2 Audio DSP already has support for four other terrestrial and satellite standards: DAB, DAB+, HD Radio, and XM Radio. For more information, see http://www.tensilica.com/news_events/pr_2009_03_30.htm

Tensilica adds new VP

Tensilica has added a key member to its executive team. Mahesh Venkatraman has joined Tensilica as vice president of marketing, vertical segments. In this new position, Venkatraman will report to company president and CEO, Jack Guedj, and is responsible for the marketing, strategic business development, and partnerships for audio, video, and baseband DSP (digital signal processing) vertical segments.

For more info, see http://www.tensilica.com/news_events/pr_2009_03_24.htm

New Bluetooth SBC Decoder and Encoder

Tensilica announced the immediate availability of the Bluetooth sub-band codec (SBC) decoder and encoder for its popular HiFi 2 Audio DSP. Now designers of cellular phones, portable music players and other devices can easily design in Bluetooth capabilities, along with over 50 other audio standards already available, that run on the HIFi 2 Audio DSP. For more information, see http://www.tensilica.com/news_events/pr_2009_02_11.htm

Tensilica Demonstrates Audio, Video and Next-Generation Baseband DSP at Mobile World Congress in Barcelona

Tensilica, Inc. will demonstrate its industry leading audio, video and baseband DSP processor cores for wireless mobile devices and base station systems at the Mobile World Congress (MWC) exhibition in Barcelona next week, February 16-19. Major systems and semiconductor companies will be showcasing products using Tensilica’s technology, and many 4G/LTE, PicoCell and FemtoCell, WiFi, mobile digital radio, and mobile digital TV baseband communications SOC designs are now in progress based on Tensilica’s customizable dataplane processors.

For more information, see http://www.tensilica.com/news_events/pr_2009_02_10.htm

UpZide Offers Expertise in VDSL2, LTE, UWB and Baseband Chip Desi

UpZide Technologies AB is now an authorized Tensilica Software Design Center. Over the past three years, UpZide has worked extensively on designs with Tensilica’s Xtensa customizable processors, and have strong expertise in optimizing these processors for VDSL2 (very high bit rate digital subscriber line), the most advanced standard for DSL communications. UpZide is now available to help other companies with their wireless datapath or baseband designs, including LTE (long-term evolution) and UWB (ultra wideband).

330HiFi Audio DSP Licensed by Fujitsu Microelectronics for Portable Consumer Electronics

“We selected Tensilica’s Diamond Standard 330HiFi Audio DSP for our customer’s portable consumer product,” stated Yoshio Kuniyasu, general manager of the IP Platform Solution Division at Fujitsu Microelectronics Limited. “Our customer realized that the Tensilica solution is one of the best for low power and had an extensive list of available software.”

For more information, see http://www.tensilica.com/news_events/pr_2009_01_27.htm

Tensilica Drives Multimedia and Communications Products at CES 2009

Over 35 companies that either license Tensilica’s popular processor cores, or use merchant market semiconductor products that include Tensilica’s cores, will be displaying products at this week’s International Consumer Electronics Show (CES). These Tensilica-enabled products include some of the most advanced, innovative consumer devices, including Blu-ray Disc players, LCD TVs, cellular phones, WiFi- and W-USB-enabled notebook computers, inkjet and laser printers.

The list of exhibitors at CES that either license Tensilica’s processor cores, or use Tensilica-powered silicon products includes: AMD, Atheros Communications, Belkin, Broadcom, Calibre Technology, Cisco, Cypress Semiconductor, Dell, Denon, D-Link Systems, DS2, Epson, Fujitsu, HP, iBiquity Digital, Intel, JVC, Kodac, Lenovo, LG Electronics, Marvell, Mediaphy, Mitsubishi, Motorola, NEC Electronics, NTT Electronics, NVIDIA, Olevia, Olympus, Panasonic, Samsung, Sony, Toshiba, Validity Sensors, XM Radio and Yamaha. For more info on their innovative products, see http://www.tensilica.com/news_events/pr_2009_01_08.htm

Tensilica Enables Single Audio Core Blu-ray Disc Player SOCs

Tensilica will demonstrate DTS-HD Master Audio Lossless decoding on the HiFi 2 Audio DSP (digital signal processor), the industry’s lowest power, most area efficient audio processor core, at the Consumer Electronics Show in Las Vegas, January 8-11, 2009. The HiFi 2 DSP offers significant cost savings and a simplified programming model, as all Blu-ray audio processing can be done in one core, unlike other solutions that require two or more cores. Tensilica will have a private suite at the Las Vegas Convention Center, South Hall 3 (second floor), meeting place #35672MP. Reserve a meeting now by emailing meetings@tensilica.com.

For more information, see http://www.tensilica.com/news_events/pr_2009_01_07.htm

RealAudio Decoder Support for HiFi 2 Audio DSPs

Tensilica has ported the RealAudio 8, 9, and 10 decoders from digital entertainment services company RealNetworks, Inc. (RNWK) to the HiFi 2 Audio DSP, the industry’s leading licensable audio DSP. RealAudio utilizes advanced audio compression techniques to allow users to achieve high quality sound in a wide bandwidth range, and is the preferred media format for many users of cellular phones, portable media players, and mobile Internet devices. For more information, see http://www.tensilica.com/news_events/pr_2009_01_06.htm