Monday, December 07, 2009
Our eighth generation tools further automate customized Xtensa dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE), and pin-level co-simulation with RTL. These enhancements further strengthen Tensilica's leading position as the highest performance, and most complete, customizable processor core solution for SOC designs.
Posted by Tensilica at 10:12 AM