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Monday, December 07, 2009

Enhanced Tools for Dataplane Processor Design and Software Development

Our eighth generation tools further automate customized Xtensa dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE), and pin-level co-simulation with RTL. These enhancements further strengthen Tensilica's leading position as the highest performance, and most complete, customizable processor core solution for SOC designs.