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Monday, September 14, 2009

Sign Up Now For EETimes SOC Online Conference Wed 9/16

Tensilica's Chief Scientist Grant Martin will participate in panel at 5 pm Eastern Time: Economics of Next-Generation SoC Design: A node too far?

The cost of both design and manufacturing is growing exponentially at each new technology node. The largest chip companies will continue to push scaling forward for the foreseeable future. But what about the rest of the field? At what point does it stop making sense for companies to move to the next node? To what degree is this a function of design and/or verification costs? In what application areas does it make sense for companies to deploy FPGA-based SoC designs. This panel will examine the state of the economics of different forms of SoC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon.

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