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Monday, December 07, 2009

Top EDA Companies Endorse Tensilica’s Pin-Level SystemC Models

Cadence, Mentor and Synopsys endorse Tensilica's pin-level SystemC models. The pin-level models are a natural extension of Tensilica's pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC), and allow designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators, and do not require the usage of any specialized hardware/software co-simulation tool.