Ap note: Implementing the Advanced Encryption Standard on Xtensa Processors

This application note examines the Advanced Encryption Standard (AES) cipher and illustrates the power of a configurable processor in accelerating encryption and decryption. Xtensa-based application-specific processors are quickly designed, simulated, and instantiated in silicon. These processors offer performance that rivals hardware solutions along with the benefits of flexibility, programmability, and ease of verification found with purely software implementations. The processor extensions proposed in this application note give the Xtensa processor a speedup of over 300x compared to a base Xtensa processor or a similar 32-bit RISC engine such as ARM9, MIPS32, etc. See http://www.tensilica.com/products/literature-docs/application-notes/tie-application-notes/advanced-encryption-standard.htm