Follow us on:
Subscribe Twitter Facebook

Thursday, September 24, 2009

White Paper: Get Your ASICs and SOCs Off the Bus!

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.

http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/