Tuesday, December 08, 2009
Tensilica Delivers New Design Flow Support for Synopsys’ Galaxy Implementation Platform Technologies
We now provides out-of-the-box automated design flow support for key technologies within Synopsys' Galaxy Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica's new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15% improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows, thus offering immediate benefits to Tensilica customers.
Posted by Tensilica at 10:19 AM