Software Porting to Tensilica-based Multicore SOC Designs now aided by PolyCore Software’s Poly-Platform

PolyCore Software, Inc. (PSI) and Tensilica, Inc. today announced a partnership to make it easier and faster for developers to port their software to, or design software for, integrated circuits with multiple Tensilica dataplane processors (DPUs). PSI's Poly-Platform toolset now comprehends Tensilica's entire DPU family, which ranges from small footprint controllers to the industry's highest-performance DSP (digital signal processor) IP core, with many variations in between.

Happy Holidays

Tensilica is Getting Ready for the Consumer Electronics Show

We had a palette wrapping party this morning, getting ready for tomorrow's shipment to the Consumer Electronics Show. We also have a huge black crate full of stuff. If you are going, be sure to set up an appointment to see our latest audio demonstrations. We're in the LV Convention Center, South Hall, booth MP25166. Email us to set up an appointment.

Four New Jobs at Tensilica

We just posted four new jobs, for a total of 18 openings around the world. Check out our careers page at http://www.tensilica.com/company/careers.htm . Jobs range from corporate controller to field application engineers to DSP engineers. We're particularly ramping up with specialists in marketing and engineering for audio.

Funitsu F-12C cel phone features Tensilica's Hifi Audio DSP

F-12C's advanced audio technology enables a wide range of features that make the handset easier to hear, including "Super HAKKIRI VOICE (extra-clear voice) 3," which enhances the clarity of the caller's voice in noisy or crowded places, and "PITTARI VOICE (exact voice)," which adjusts the phone's audio to the proper volume based on the user's body movements when walking or running. As well, the smartphone is equipped with a voice balance feature that automatically accentuates the high-pitched portions of the sound of the other person's voice, making it easier to hear. Find out more.

White Paper: Optimize SOC Performance Using Memory Tuning and System Simulation

Memory tuning allows you to choose memory-related parameters for each on-chip processor core that balance system performance, processor area (cost), and memory size by exploring a target application's sensitivity to these memory-system parameters. The processor core's instruction-set simulator (ISS) plays a key and central role in this assessment because the ISS can model and report the expected system performance, providing a breakdown of memory-related stalls. Read the white paper.

White Paper: 7 Critical Questions to Ask When Selecting a Digital Audio Solution for SOC Design

The complexity of delivering a mobile audio IP solution to SOC designers causes design teams to ask many, many questions before choosing an audio core and associated codecs. That's a good thing. The selection process is complex, and the more information you have before making the decision, the better. Experience shows that design teams' questions about mobile audio solutions fall into seven broad categories. Check out this white paper.

Tensilica Signs RacyICs as New Authorized Design Center Partner for IC Design

RacyICs offers integrated circuit design, verification and implementation services.

“We were very impressed with Tensilica’s technology offering and the rapid rate of adoption of their products in Europe,” stated Jens-Uwe Schluessler, managing director, RacyICs. “By building an expert knowledge of Xtensa, in combination with our experience in power management, we can provide customers the optimal DSP or processor for their application.” See press release

Missed Tensilica's Israel Seminar "Customizable DSP IP Cores Made Simple"?

If you didn't get to our seminar in Isael, here's your chance. You can see the presentations on our web site.

Skyviia Chooses Tensilica's HiFi Audio DSP

"We selected the HiFi Audio DSP because it had the best combination of high performance, speed, and low power," stated Brian Sung, executive vice president  Skyviia. "And we were particularly impressed with the huge library of audio codecs already ported and optimized for this architecture."
See press release.

Paul McLellan Discusses How to Use Processors in the SOC Dataplane

Tensilica's DPUs are idea for the SOC Dataplane. What's a DPU? Read this article. The main advantages are:

• Flexibility. Changing the firmware changes the blocks function.
• Software-based development, with lower cost tools and ease of making last minute changes.
• Faster and more powerful system modeling, and more complete coverage
• Time-to-market
• Ability to make post-silicon changes to the firmware to tweak/improve algorithms
• DPU processor cores are pre-designed and pre-verified. Just add the firmware.

Read Tensilica's CTO Chris Rowen's New Blog on ROI and Running a Marathon

Entrepreneurship has a lot in common with running marathons. It may seem like a simplistic cliché, but the analogy works at multiple levels. Read this blog to find out why.

Tensilica's Seminar in Israel Nov. 17 "Customizable DSP IP Cores Made Simple"

Visit this seminar to find out about Tensilica’s wide range of DSP IP cores. Tensilica actually has more varieties of DSP IP cores than any other vendors, plus we offer you the ability to easily customize our base processor for the DSP functions you need for your application.

Our base processor is also an excellent controller, allowing you to do the control functions along with the DSP functions or even use it as a software tools compatible controller for your chip design.

From a basic 2-MAC DSP all the way up to the fastest DSP in the industry, our 128-MAC baseband processor for LTE Advanced, Tensilica can help you get the DSP performance you need in a highly efficient IP core. Sign up now!

Tensilica's Extensive Partner Ecosystem - Have You Looked at it Lately?

Take a good look at our list. Whether you're looking for audio enhancement SW from parters Dolby, DTS, QSound, AM3D, SRS, or Audyssey or a partner to help with your SOC design - we have so many different partners that can help you get your design done faster. Check out the list.

Tensilica's Korean Office Moved.

New address:
#201, DeungWoo Bldg.
127-11, Samsung-dong, Kangnam-gu,
Seoul, 135-875, Korea
Tel: 82-2-6007-2745
Fax: 82-2-6007-2746

Tensilica white paper: 10 Resons to Customize a Processor Core

There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. We'll give you 10 good reasons why you should consider customizing your core in your next SOC design.
Read the white paper.

Trick or Treat at Tensilica Today

 

Here are two of the cutest witches who came to visit Tensilica today. Yes, it's our annual bring-your-kids to Tensilica day for trick-or-treating.

EnVerv Selects Tensilica ConnX DSP for Smart Grid Power Line Communications

“We picked the ConnX DSP core because of its flexible architecture and excellent processing power,” stated Dr. Farrokh Farrokhi, executive vice president of engineering at EnVerv. “By using the ConnX DSP we were able to reap the benefits of implementing custom instructions that are unique to our signal processing algorithms, thus giving us the benefit of a custom DSP design while maintaining the flexibility of a soft architecture.” Read the press release.

Tensilica's Booth at the TSMC Open Innovation Platform Partners Event

Here we are at the TSMC Partners event. Tensilica showcased its audio DSP with demos of QSound and SRS audio enhancement packages.

See Tensilica Tomorrow at TSMC Open Innovation Platform Ecosystem Forum

Yes, we'll be at the San Jose convention center from 8 am to 6:30 pm in booth 104. See you there!

White Paper: How to Increase ASICs and SOC Computational Performance with Long-Word Processors

VLIW processors execute multiple independent instructions each clock cycle and provide a tremendous performance boost per clock cycle without incurring the exponential power-consumption increase caused by clock-rate increases. However, VLIW architectures have their own problems, particularly code bloat, which causes code footprints to balloon-thus increasing memory costs.

The Xtensa LX processor uses an innovative approach to VLIW design called FLIX (Flexible Length Instruction eXtensions), which gives ASIC and SOC designers more options for cost/performance tradeoffs. FLIX technology provides the flexibility to develop ASIPs (application-specific instruction-set processors) that freely and modelessly intermix smaller RISC instructions with multi-operation FLIX instructions. Read our white paper.

IntegrIT's DSP Math Library Ported to Tensilica's Baseband DSPs

The IntegrIT NatureDSP Math library simplifies the software development process for design teams that want to port their own signal processing application software to the ConnX BBE16 DSP.  The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for implementation of typical digital signal processing functions including highly optimized routines for filtering, FFT, matrix, trigonometric and other math operations.
Read the press release.

White Paper: Optimizing a DSP Architecture for Wireless Baseband

The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations. Read the white paper.

Tensilica Participates in Synopsys TLMCentral Web Portal for Transaction-Level Model Access

TLMCentral aggregates information about free and commercial system-level models of common system-on-chip (SoC) components from leading semiconductor IP vendors, tool providers, service companies and universities. TLMCentral is an open portal that will ease and accelerate the development of virtual prototypes across the industry. It is available at no cost to users and providers of transaction-level models.

Transaction-level models raise designer productivity by increasing the level of abstraction at which they design. TLMs are predominantly used in virtual prototypes which allow engineers to accelerate their software design schedules by up to nine months and significantly improve the productivity of their software development, hardware/software integration, and system validation tasks. Transaction-level modeling has also contributed to significant productivity gains in architecture design and SoC verification, and the models aggregated on TLMCentral can be applied to those use cases as well. See Synopsys news.

Software Defined Everything - Tensilica's Grant Martin's latest blog

Tensilica's Chief Scientist Grant Martin discusses the challenges of getting the right mix of hardware and software for hardware defined radios. Read his blog post.

Fraunhofer ISS is Tensilica's Newest Authorized Design Center Partners

Wow. If you need someone with tons of experience in audio and multimedia technologies, look at Fraunhofer.

“We look forward to working closely with Tensilica and the wide customer base using Tensilica’s HiFi Audio DSPs, especially for home entertainment, automotive and mobile multimedia,” stated Marc Gayer, head of Embedded Audio at Fraunhofer IIS. “Tensilica’s HiFi Audio DSP architecture is extremely efficient with industry best area and power requirements.” See press release.

Tensilica Now Hiring in Israel

We're looking for a great Field Applications Engineer. Learn more about this posting here.

Visit Tensilica's Linux Wiki Pages

Yes, several Tensilica customers run Linux on their Tensilica IP cores. And we collect information on how best to do that at our Wiki. We've seen Linux running on cores with up to a gigabyte of memory. And while most of our processors run without operating systems in the dataplane, why not match up those dataplane cores with a Tensilica main control processor running Linux as well. Then all the cores will be using the same software tool chain.

Tensilica Customer TranSwitch Announces LTE™ Fixed Wireless Residential Gateway Solution

Last week TranSwitch announced the availability of a new LTE (*Long Term Evolution; a 4G wireless broadband technology) fixed wireless reference design that enables wireless providers to deliver broadband voice, video and data services to homes and enterprises. TranSwitch’s reference design incorporates its Atlanta 2000™ processor and complete software solution which is designed for high performance, real time services under real world network conditions.  The Atlanta 2000 includes Integrated dual RISC cores: 400 MHz Tensilica Xtensa LX with MMU.

Three More Jobs Posted at Tensilica

Check out our full list (we're up to 17 jobs posted now) and see if you know someone that can help Tensilica grow. We're looking for people in Beijing, Pune and Santa Clara.

SRS Labs Expands Portfolio of Advanced Audio Solutions Available for Tensilica HiFi DSP Cores

"Tensilica's HiFi 2 and HiFi EP DSP cores are the popular choice of our platform partners," said Joanna Skrdlant, Senior Director, Global Platform Partner Program. "Over the course of a year, we've seen a substantial increase in our licensee's projects based upon chips designed with Tensilica HiFi 2 and HiFi EP DSP core solutions. Given this accelerating demand, we made it a top priority to port our latest audio technologies to the HiFi cores."

See the full press release and details here.

Cavium Picks Tensilica for Next-Generation Wireless Broadband Application

 The Tensilica products selected include Tensilica's popular baseband IP specialized for channel decode applications and signal processing to achieve best-in-class speed, power and performance. Cavium is a leading provider of semiconductor products that enable intelligent processing for networking, wireless, storage and video.

"Tensilica's IP will help us achieve best-in-class speed/power/performance, faster time-to-market and great flexibility through efficient programmability," stated Raj Singh, general manager, Wireless Broadband Group, Cavium. "We were particularly delighted with Tensilica's understanding of the computational processing required for wireless broadband and their great technical support."

See press release.

This Week - Tensilica Seminars in Taiwan and Japan

It's last chance time to sign up for Tensilica's seminars in Taiwan on Sept. 14 and in Japan on Sept. 16. Visit this seminar to find out about Tensilica’s wide range of DSP IP cores. Tensilica actually has more varieties of DSP IP cores than any other vendors, plus we offer you the ability to easily customize our base processor for the DSP functions you need for your application.

Our base processor is also an excellent controller, allowing you to do the control functions along with the DSP functions or even use it as a software tools compatible controller for your chip design.

From a basic 2-MAC DSP all the way up to the fastest DSP in the industry, our 128-MAC baseband processor for LTE Advanced, Tensilica can help you get the DSP performance you need in a highly efficient IP core. As examples of the performance you can get from our technology, we’ll showcase our audio and baseband DSPs in this free seminar.

Audyssey’s Sound Correction Technologies Come To Tensilica’s HiFi Audio DSP

Audyssey's audio technology fixes acoustical and perceptual problems to reproduce content as close to the original as possible. This helps ensure that consumers get the best sound from their home theaters, DTVs, automobiles and mobile devices. Audyssey's technology provides expanded surround sound options, preserves immersion at low volumes, helps eliminate distortion, maintains optimal volume when people watch TV, and can even prevent low frequencies from disturbing the neighbors. Read press release.

EtherWaves Expands Digital Radio Choice – Adds Support for Tensilica Dataplane Processor Cores

The new ClearSignal RF agnostic design broadens SoC designers' choice to immediately add Digital Radio capability to mobile devices, while keeping the required low power consumption. This ClearSignal implementation takes advantage of Tensilica's ConnX Vectra LX DSP Engine and other architecture optimizations for achieving a typical DAB channel reception at clock rates as low as 50 MIPS. Read the press release for more details.

Tensilica's Xtensa 9 or Xtensa LX4? What's the difference in Customizable Processors?

Xtensa LX4 is built on top of the Xtensa 9 architecture, so it's important to evaluate both to see what processor is best for your application. This page has an interesting comparison between the two.

White Paper: 10 Tips for Successful SOC Design

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.

Look to Tensilica for the Widest Range of DSP IP Cores

Everybody's DSP requirements are different. Instead of trying to figure out how to squeeze your requirements into a DSP core that doesn’t quite match your needs, Tensilica gives you lots of choices - as a matter of fact, Tensilica offers an almost unlimited range of DSPs. How can we do this? You can pick from several pre-defined function blocks in our ConnX DSP family or you can design your own to exactly match your application. Find out more.

Check Out Tensilica's Job Listings - We need HW, SW, and DSP Engineers

We just added to our extensive listing of jobs in Pune, Beijing and Santa Clara. Check out the full listing. Do you know any good Software build and QA engineers? How about Baseband DSP software? We're growing right now and hiring as fast as we can find good candidates.

Sign Up Now for Tensilica's Sept. 14 Taiwan Seminar

Learn more about Tensilica's DSPs and DPUs (dataplane processing units) and how these can help you develop chips that are lower power and higher performance than other IP cores. Sign up now.

Read EETimes Article about Tensilica CTO Chris Rowen's HotChips Paper

This article showcases the ConnX BBE64, which combines SIMD and VLIW concepts and lets designers configure processors for a range of handset and base stations uses.

"We are trying to build a world-leading DSP core, arguably the fastest DSP core yet," said Chris Rowen, Tensilica founder and chief technologist in a talk at the Hot Chips event here.

Tensilica Needs Applications Engineers

As a matter of fact, Tensilica has a record number of job postings now in several categories, from a corporate attorney to HW and SW engineers. These jobs are located in Pune, Beijing, and Santa Clara. Check out the full list.

Guide to using Tensilica's Cores in the SOC Dataplane

Designers have long understood how to use a single processor for the control functions in an SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That's why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and verify, and are not programmable to handle multiple standards or changes. Read this section of our web site for the latest tips on using processors in the SOC dataplane.

See Tensilica CTO Chris Rowen's Fast DSP Presentation at HotChips Thursday, 4:15 pm

Chris Rowen, CTO and founder of Tensilica, will present, “The World’s Fastest DSP Core: Breaking 100 GMAC/s Barrier,” at the HOT CHIPS 23 symposium in Stanford, CA, on August 18.  Dr. Rowen will discuss the accelerated transition to 4G wireless connectivity through LTE and LTE-Advanced that mandates a more programmable baseband architecture.  He will disclose the rationale, machine organization, and instruction set of the Tensilica ConnX BBE64 family, a high-performance SIMD/VLIW digital signal processor built for 4G cellular systems. 

Read Tensilica CTO Chris Rowen's Blog about HotChips 2011

The HotChips conference August 17-19 at Stanford University is well respected as the foremost conference about new innovations in processors for chip design. Chris Rowen gives his enlightened perspective of what to look for, including the battle for mainstream processor architectures, new technologies, and talks on higher levels of system integration. See his review in his blog on Low-Power Engineering.

See Tensilica at the Flash Memory Summit, 8:30 Thursday AM (tomorrow)

Neil Robinson's presentation will be about how the processor choice affects both data management tasks and computational throughput. He really pinpoints the difference between Tensilica's processors and other cores - how our processors were designed from the ground up to be ideal for the compute-intensive dataplane functions (others designed for control). Stop by and listen if you're going to this conference.

Take Advantage of Nintendo's Price Cuts to Get Tensilica Inside 3DS Game

Nintendo has dropped the price of it's 3-D handheld game, so now it's one of the most fun ways to get a consumer product with Tensilica inside. And while this price drop is supposed to be effective August 12, rumor has it you can get it from Walmart now. Additionally, starting September 1 they will start giving away some games for free. So get yours now.

Tensilica's HiFi Audio DSP Does All of the World's Digital Radio Standards

Designers of digital radio systems can use one processor core - Tensilica's HiFi 2 Audio DSP - to run all of the decoders required throughout the world for digital radio, enabling a universal worldwide digital radio receiver. Tensilica's HiFi2 Audio DSP supports all of the terrestrial and satellite standards: DAB, DAB+, HD Radio, DRM, and XM Radio. See our chart of all standards and what we have to offer.

Tensilica's Fall Seminar in Japan - Sept. 16, 2011 - Register now!

Want to learn more about Tensilica's audio and baseband products? Sign up now for our fall seminar in Japan. And stay tuned for news about our seminars in Taiwan and Israel. See our events page.

LG Electronics Picks Tensilica’s HiFi Audio DSP and SW Codecs for HDTV

"We picked the HiFi Audio DSP for its speed, power, and performance, its C-based programming model, and its completeness as a turnkey solution, including both the hardware and the software codecs we need for medium and high-end DTVs," said Seung Jong Choi, Vice President, LG Electronics. "Moreover, Tensilica offers us an attractive, automated process to customize the HiFi Audio DSP and add our own algorithms to further differentiate our products in highly competitive markets."

Great White Paper from Tensilica

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.

Get a New Computer for School with Tensilica Inside

All you need to do is get a computer with an AMD Radeon Graphics chip or card inside. Like the new Apple iMacs, or many PCs and notebooks.

Read What BDTI Says about Tensilica's ConnX BBE64 for LTE Advanced

Cellular networks delivering 1Gbps of raw data throughput are on the horizon, and Tensilica is designing a DSP to meet the baseband-processing requirements of such networks: the ConnX Baseband Engine 64 (BBE64). The BBE64 achieves its performance by employing wide execution units that support up to 128x 18-bit operations in parallel, wide 640-bit registers, and massive I/O. The company targets a performance increase of 5-15 times for the BBE64 compared with the currently availablwe BBE16 for LTE.
Read more.

Design Art Networks Announces Tensilica-based Small Cell LTE Reference Designs

Our partner, Design Art Networks (DAN), announced yesterday the availability of several complete compact base station reference designs for compact, low-cost, carrier-grade LTE small cell products.
Ready for immediate productization, DesignArt Networks has tested and released a fully integrated and standards compliant 3GPP LTE PHY software solution, for LTE and LTE Advanced small cell deployments. Combined with the available Unified Mobile Backhaul software pack, DAN3000 base station reference designs represent a fully integrated single-SoC LTE Advanced small cell base station with unified self-backhaul and relay. Read more about this.

Happy Anniversary to Me

It's been 9 years now since I joined Tensilica. Wow, a lot has happened during that time. We went from Xtensa 4 to Xtensa 9, added HiFi Audio DSPs and the ConnX family of baseband DSPs. Started going to the CES and Mobile World Congress trade shows. I was even able to convince the company to install Salesforce and led that project.

Now, as I see the fruits of all this work, things are really looking good around here. We just celebrated shipping our billionth IP core, and we're on target to get to 2 billion cores by the end of 2012. We're hiring like crazy (check out our careers page). Business is good, and I'm glad I stayed. Looking forward to several more good years ahead.

White Paper: Cut DSP Development Time – Get High Performance From C, No Assembly Required

Designers are asking their DSP cores to do more and more of the heavy workloads required for highly complex algorithms for filtering, FFT, MIMO, and other signal processing intensive applications. To get high performance from a conventional DSP core, developers have traditionally used assembly code programming, which is time consuming and difficult to debug.

Advances in state-of-the-art DSP architectures and companion compilers now make it possible for developers to keep their algorithms in C and still get the performance they need from a general-purpose high-performance DSP.

The magic is in the compiler technology. This white paper explains how Tensilica's ConnX D2 DSP engine coupled with the advanced Tensilica XCC compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code. The result: you can get your project finished much faster.

Tensilica Hat Spotted at Wimbledon!

Here's Mrs. Tim Penhale-Jones wearing her Tensilica hat at the ladies final day, centre court Winbledon. Where do you wear your Tensilica hat? Email me a picture and I'll be proud to post it. She's the wife of our European sales director and I'm sure she has a first name but I don't know it. Do you need a hat to take on your next adventure? Send me an email.

New Job Posting: Staff Logic Design Engineer in Santa Clara

We're hiring lots of engineers (and one corporate attorney) in Santa Clara, Pune, and Beijing. Keep checking our Careers page for the latest updates. We're growing!

Newest SOC Design Partner: Dream Chip Technologies (DCT)

Welcome DCT - our newest design center in Garbsen, Germany. They have extensive Tensilica expertise, particularly in low-power multimedia designs. They really know their TIE, and can help our customers get the lowest possible power and most efficiency with their customizable processor designs.

White Paper: Using Processors in the SOC Dataplane

To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines.This is a great white paper to help you understand how you can apply processors for dedicated functions in the dataplane.

Looking for the Best PC Graphics?

Tensilica's processors configured to accelerate video stream decoding are an ingredient in every UVD-powered AMD ATI graphics chip, including those with ATI Avivo HD video and display technology, which provdes PC users with crisp images, smooth videos and true-to-life colors. UVD is a dedicated video decode processing unit that offloads the CPU from the decoding process. UVD technology reduces power use, helps decrease system noise and helps to increase notebook battery life during HD video playback. AMD's graphics products provide for DirectX10 and DirectX11 gaming and allow PCs to be hooked up to big-screen TVs with HDMI and built-in 5.1 surround sound audio to enjoy Blu-ray and HD DVD movies.

UVD-powered AMD ATI graphics chips include the HD5000 serires, HD4000 series, the HD3000 series, the HD2000 series, the x1900 series, the x1600 series, and the x1300 series.  See some of them at our web site.

Good Summer Reading: Using Processors in the SOC Dataplane

To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines. With a DPU's programmability, designers now have the flexibility to make changes close to and after silicon production. This white paper explains how DPUs can be effectively used in the SOC dataplane.

Use Tensilica's Processor Customization Tools for University Research

Join the growing list of universities who are using Tensilica's processor generator tools in the classroom and for research. Universities around the world are participating in this program. We're working with universities in Australia, Canada, China, all over Europe, India, Japan, South Korea, Mexico, the Middle East and Africa, New Zealand, Russia, Singapore, South America, Sri Lanka, and Taiwan. Check out our program.

White Paper: How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors

Some video frames take longer to process than others because of the nature of digital video compression. These wide variations in video-processing time make correct operation of an ASIC or SOC video-processing system unpredictable. A video processor that minimizes processing-time variations in for each video frame enables the design of a more reliable and less expensive system that also consumes less power. Read this white paper to find out how you can efficiently process video grames.

New WMA 10 Pro Lossless Decoder for Tensilica's Popular HiFi Audio DSP Core

The Windows Media Audio 10 Professional (WMA 10 Pro) Lossless decoder implements the full WMA 10 Pro decoder and adds the creation of a bit-for-bit duplicate of the original audio file so that no data is lost. Different profiles cover bit streams ranging from 44.1 kHz stereo streams to 192 kHz 7.1 streams. In addition the decoder supports lossy profiles that include everything from full-resolution 24-bit/96 kHz audio in stereo, to 5.1- or 7.1-channel surround sound, to highly efficient mobile capabilities at 24 Kbps to 96 Kbps for stereo, and 128 Kbps to 256 Kbps for 5.1-channel sound.

It's been optimized for maximum exfficiency on Tensilica's HiFi Audio DSP cores. Check it out.

White Paper: Everything You Wanted to Know About Blu-ray Audio, but were afraid to hear

Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.

Take Your Kindle With You on Vacation

And you'll be taking Tensilica with you. Tensilica's inside the Amazon Kindle readers. Enjoy your vacation and your Kindle!

What are Tensilica's Engineers So Interested In?

What are they watching with such great attention? Yesterday's Field Application Engineering training ended in go kart races! Get your engines ready!

Great EE Times Article on Tensilica Shipping a Billion Cores

Have you read this yet? Clive "Max" Maxfield has a great write-up. He writes, "This is all quite exciting and mind-boggling at the same time."

White Paper: Get the performance you need from your DSP core, even when programming in C

Designers are asking their DSP cores to do more and more of the heavy workloads required for highly complex algorithms for filtering, FFT, MIMO, and other signal processing intensive applications. To get high performance from a conventional DSP core, developers have traditionally used assembly code programming, which is time consuming and difficult to debug.
Advances in state-of-the-art DSP architectures and companion compilers now make it possible for developers to keep their algorithms in C and still get the performance they need from a general-purpose high-performance DSP. Read this white paper to find out more.

Tensilica Licensees Ship One Billionth IP Core

And we're projecting we will ship 2 billion cores by the end of 2012. Tensilica’s licensees are currently shipping at a run rate exceeding 500 million Tensilica DPUs per year, and Tensilica projects its customers will hit the two billion cumulative shipment mark by the end of 2012 – a doubling in volume in just 18 months.

“Tensilica is at a point where the company could really take off,” stated Will Strauss, president of Forward Concepts and leading DSP analyst. “It quickly jumped to a formidable position in baseband DSP IP cores for LTE and has the leading audio DSP core. And their customers really appreciate the ability to customize the cores for their exact applications.”