Guide to using Tensilica's Cores in the SOC Dataplane

Designers have long understood how to use a single processor for the control functions in an SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That's why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and verify, and are not programmable to handle multiple standards or changes. Read this section of our web site for the latest tips on using processors in the SOC dataplane.