White Paper: Optimizing a DSP Architecture for Wireless Baseband

The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations.

The ConnX Baseband Engine is a configuration option package for Tensilca's Xtensa LX customizable processor core. It implements a 3-way VLIW, 8-way SIMD architecture that can sustain 16 multiply-add operations per second and performance of a full radix-4 FFT butterfly per cycle. At 400 MHz, it provides almost 13GM per second of memory bandwidth and 1.6B complex FIR filter taps per cycle. It directly implements 8-way parallel division and 4-way parallel reciprocal square root operations.  And up to eight ConnX Baseband Engines can be used together for maximum performance.

The rich programming environment, including vectorization of scalar C applications, allows easy deployment of into complex applications.  In addition, the Xtensa processor family, including the ConnX Baseband Engine, supports easy integration of multiple cores with high-bandwidth memory and direct port interconnect among each tightly-coupled cluster of cores.

The ConnX Baseband Engine is specifically designed for digital television, cellular basestation, femto-cell and other software-agile radio applications and is also being used to provide full programmability for  multi-standard broadcast receivers.

See Tensilica at SNUG - Synopsys Users Group

Tonight we'll be at the Vendor Fair and tomorrow afternoon we're in a tutorial "Extending Design Flows to the System-Level – How ESL Fits into Your Design Flow!" Click on the headline link to find out more about the tutorial session.

ConnX D2 Delivers Outstanding 16-bit Fixed Point DSP Performance on Compiled C Code

No need for assembly code optimization. This allows SOC development teams to have greater flexibility in resource allocation as well as the ability to quickly change algorithms. C code optimized with TI C6x or ITU C intrinsic functions compiles directly to the ConnX D2 instruction set, allowing developers to benefit from pre-existing TI and ITU code bases.

The ConnX D2 option adds dual 16-bit multiply-accumulate (MAC) units and a 40-bit register file to the base RISC architecture of the Xtensa LX processor. The ConnX D2 engine utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code. It also delivers dual-MAC performance using 64-bit VLIW (very long instruction word) instructions for code that cannot be vectorized.

White paper: Get your ASICs off the Bus

Bypass the bus altogether with GPIO and FIFO-like interfaces from Tensilica's processor cores. Read about how this significantly speeds data through the processor in this white paper.

See pics of NTT DOCOMO's demo at MWC of their LTE Platform

Tensilica's enabling next-generation LTE and 4G handsets. See pictures of NTT DOCOMO's demo at MEC of their LTE platform with multiple Tensilica Xtensa processors inside.

Diamond 570T - our Highest Performance Controller per EEMBC Benchmarks

It combines an efficient 5-stage pipeline with a 3-issue VLIW architecture, enabling it to obtain leading performance levels on both control and DSP code.

The Diamond 570T features innovative I/O that allows data to be streamed in and out of the processor without going over the main data bus. The two 32-wire GPIO (general-purpose I/O) ports allow direct control and monitoring of peripherals. Two 32-bit FIFO port interfaces can connect to standard FIFOs for direct, predictable communication with other RTL blocks, devices and processors.

IntegrIT Joins Tensilica’s Xtensions Partner Network for DSP Software Services

IntegrIT DSP Design House, a leading supplier of DSP software solutions, has joined Tensilica's Xtensions partner network to provide vital software components, including the high-performance Nature DSP Signal+ library, for the ConnX Baseband Engine, HiFi Audio DSPs and the ConnX D2 communications DSP.

The IntegrIT Nature DSP Signal+ is a collection of signal processing functions that assist the implementation of typical DSP algorithms. All functions are optimized for, and utilize, the full data bus bandwidth and computing power of each of the ConnX DSPs. The IntegrIT Nature DSP Signal+ library features over 30 common math and signal functions and is designed to be useful in practical real-time DSP applications.

Multiple Tensilica IP Cores Power NEC, Fujitsu and Panasonic Mobile Communications Fully Functional LTE Handset SOC

NTT DOCOMO has confirmed that several Tensilica Xtensa LX dataplane processor cores (DPUs) are used in the latest LTE (Long-Term Evolution) mobile handset system-on-chip design demonstrated in February at the Mobile World Congress (Barcelona, Spain). NTT DOCOMO previously exhibited the device developed under a collaborative project among DOCOMO, Fujitsu, NEC and Panasonic Mobile Communications (Panasonic Mobile), who will deploy the chip for their LTE handsets and datacards.

Spotlight on Diamond 106Micro - Our Smallest Controller

The Diamond Standard 106Micro CPU is a cache-less 32-bit controller ideal for designers looking for a basic 32-bit controller, particularly for those migrating up from an 8- or 16-bit controller. Designed for applications with requirements for minimal size and low power, the Diamond Standard 106Micro controller enables SOC architects to quickly integrate this efficient CPU in their designs.

Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline so it can achieve 650 MHz in 65gp process and up to 900 MHz in 45gs process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves much higher code density than other 32/16-bit architectures.

CTO Chris Rowen Speaking at Silicon Valley IEEE SSCS

Dr. Rowen will be talking about "Ultra-Low-Power Software-Defined Radio for LTE Wireless Baseband" at the Silicon Valley IEEE Solid State Circuits meeting this Thursday, March 18. Meeting open to everyone.

New 3rd Gen Diamond Controllers

This family of five upward-compatible processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today's compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption.

Why Designers Need a New DSP for SOC Designs

The rapid changes in wireline and wireless communications, disk drives, home entertainment devices, and computer peripherals are driving demand for 16-bit fixed-point DSPs. Stand-alone DSP chips are no longer cost effective for most of these price-sensitive applications. Instead, there's growing demand for general-purpose 16-bit DSP engines that can be easily designed into highly integrated SOC silicon.

At the same time, the growth of multiple standards and the complexity of these standards is driving developers away from traditional assembly-code programmed DSPs towards integrated architectures that combine excellent DSP performance with generalized high performance when developing with compiled native C control code.

The market needs a DSP engine that can easily be customized if necessary, integrated into a SOC design, and programmed most often in C, rather than assembly code. This will help speed new products to market as quickly as possible.

There's a Great Way Around the Slow Processor Bus

Read our white paper to learn how you can bypass the bus using our ports (like GPIOs) and queues (like FIFOs) to directly connect processors, much like you would connect RTL blocks.

Congratulations Cisco on Your CRS-3 Announcement

When Cisco needs to design chips for their fastest routers, they've turned to Tensilica's cores. We're delighted to see that, once again, Cisco is pushing the envelope and developing the next generation network infrastructure products that we definitely need.

Match Processor to Task by Automatically Generating the Processor Core

Read our white paper. You can use our XPRES Compiler to analyze your C code algorithm and suggest the processor changes that will accelerate that algorithm. Then, when you've optimized your processor, Tensilica will automatically generate the matching software tools that take advantage of all of your optimizations. Nice.

CTO Chris Rowen Speaking at DATE Conference Next Week

DATE is March 8-12, 2010, in Dresden, Germany. Dr. Rowen is speaking at 3 sessions:

Session 7.1 "Fabulous, Frightening and True: Stories of Multicore SOC Design for Wireless Baseband", Wed. 3/10/2010 14:30-16:00.

Panel 2.8 "Are we there yet? Has system assembly from IP blocks become like connecting LEGO blocks?", Tue., 3/09/10 11:30-13:00

Panel 10.8 "Embedded Software Testing: What Kind of Problem is This?", Thu. 3/11/10 8:30-10:00

FFT Ap Note

This ap note shows the results and design methodology for a high-performance DSP sample application on the Xtensa microprocessor using a widely known example, the Fast Fourier Transform (FFT). This note first explains the basic algorithm and how several TIE language instructions were created to implement the FFT algorithm. Performance results follow, with a comparison of implementations of the radix-2 decimation-in-frequency FFT with and without additional TIE language extensions.

Fast OFDM Ap Note

This application note looks briefly at fast signal processing for wireless modems. In particular, this application note describes the TIE (Tensilica Instruction Extension) language instructions that accelerate the complex FFT and FIR operations that dominate many OFDM channel modulation and demodulation systems.

Why High MHz Doesn't Necessarily Mean High Performance

Read our white paper. Traditionally, performance has been associated with higher frequency. However, higher performance can be achieved even while running the processor at lower frequency. This leads to not only lower power, but also to better architecture-performance efficiency and lower area. This lower area in turn leads to even more power savings when compared to traditional deep-pipeline RISC processors.