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Monday, October 24, 2005

New Ultra-low-power Xtensa 6 Processor

Tensilica's new Xtensa 6 configurable and extensible processor core for system-on-chip (SOC) design replaces Tensilica's workhorse Xtensa V processor. Xtensa 6 adds three major enhancements: the ability to automatically customize it from a C/C++ based algorithm using Tensilica's proven XPRES Compiler; approximately 30 percent lower power than Xtensa V; and advanced security provisions in MMU-enabled configurations through a "no execute" bit that provides enhanced protection against malicious code.

"Xtensa 6 provides SOC designers with the fastest, most cost-effective SOC block design tool in the industry," stated Steve Roddy, vice president of marketing, Tensilica. "By using our popular XPRES Compiler, in less than an hour designers can create application-specific building blocks that can serve as either conventional control processors or as a suitable alternative to RTL-based hardware block design, but in a fraction of the time and without the verification headaches. We expect this product to significantly widen our customer base because it fully automates time-and-resource intensive IC design steps and adds programmability to the post-silicon design, a crucial value-add enabler in fast-moving, high-volume SOC markets."

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