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Friday, April 22, 2005

sci-worx to use Xtensa for Video Cores

sci-worx will be designing several system-on-chip (SOC) intellectual property (IP) blocks, including H.264, WMV-9 and MPEG-2 for High-Definition TV, with multiple Tensilica Xtensa LX configurable processors.
Current generation IP solutions from sci-worx were designed with Register Transfer Level (RTL) logic methodologies. By adding a configurable processor-based design approach to its portfolio, sci-worx will speed design time and enjoy more flexibility to offer easier upgradability through software.

In addition to designing with Tensilica’s Xtensa configurable processors, sci-worx will become Tensilica’s first value added reseller (VAR), distributing Tensilica processors as part of larger sci-worx IP subsystems. sci-worx customers will be able to sign one license agreement with sci-worx that includes the necessary provisions for licensing the Xtensa processors inside sci-worx designed IP blocks.

“The market requirement for multi-standard video codecs for SD and HD resolutions requires more flexible solutions to address the high volume consumer market,” stated Young-Hun Kluge, vice president of sales and marketing, sci-worx, “We’ll be able to get new IP out substantially faster and provide greater flexibility to our customers by using Xtensa processors instead of traditional RTL design methods.”

“sci-worx is an excellent example of a company that understands the benefits of using processors instead of hard coding algorithms into logic gates,” stated Steve Roddy, Tensilica’s vice president of marketing. “We look forward to working as a partner with sci-worx as they complete their new IP designs.”

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