Tuesday, July 27, 2010
White Paper: Why High MHz Does Not Mean High Performance
Traditionally, performance has been associated with higher frequency. However, higher performance can be achieved even while running the processor at lower frequency. This leads to not only lower power, but also to better architecture-performance efficiency and lower area. This lower area in turn leads to even more power savings when compared to traditional deep-pipeline RISC processors. Read this white paper to find out more
Wednesday, July 21, 2010
Use Customizable Processors as SOC Building Blocks
General-purpose microprocessor cores can’t deliver the application throughput, cost, and power efficiency needed for most computationally demanding embedded SOC tasks. These processors aren’t designed to efficiently manipulate audio, video or network packets or do other highly specialized tasks.
Until now, these demanding tasks had to be hard coded in RTL to get the speed required. However, designing millions of gates in RTL takes too long, is too hard to verify, and can’t be changed once the chip is fabricated.
Now there’s a real alternative to RTL design. You can use configurable, extensible Xtensa processors instead of RTL to finish your design much faster and add flexibility to adapt to changing standards or product requirements. Tensilica’s Xtensa processors provide both the I/O throughput and the computational performance previously only available with RTL design.
Until now, these demanding tasks had to be hard coded in RTL to get the speed required. However, designing millions of gates in RTL takes too long, is too hard to verify, and can’t be changed once the chip is fabricated.
Now there’s a real alternative to RTL design. You can use configurable, extensible Xtensa processors instead of RTL to finish your design much faster and add flexibility to adapt to changing standards or product requirements. Tensilica’s Xtensa processors provide both the I/O throughput and the computational performance previously only available with RTL design.
Tuesday, July 20, 2010
Chelsio Communications licenses Tensilica's Xtensa processor
Chelsio Communications, Inc., of Sunnyvale, Calif., has licensed the Xtensa LX customizable DPU (dataplane processor) for its next-generation 10Gb Ethernet Terminator ASIC. Chelsio has used Tensilica's Xtensa DPUs in two previous generations of Terminator ASICs.
Monday, July 19, 2010
8 Years at Tensilica
Sometimes it's very hard to believe that I joined Tensilica 8 years ago last Saturday. I've seen a lot of growth in that time. Why do I stay? It's honestly a good job. We do a lot of creative things around here. I work with smart people. And the product is technically great.
Thursday, July 15, 2010
Tensilica in Home Entertainment Systems
You can find Tensilica's cores in many home entertainment systems. We picked out 4 of the most interesting applications to give you more detail: Blu-ray Disc, set-top boxes, digital TVs, and digital radio.
Wednesday, July 14, 2010
New job posting: Baseband Biz Dev Mgr
We actually have 10 positions open at Tensilica now - we're really growing and investing in new areas, like Baseband where we've seen significant success with our ConnX BBE16 baseband DSP. If you know anyone good for this or any of the positions, let us know.
Monday, July 12, 2010
White Paper: Using Processors in the SOC Dataplane
To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines. Read this white paper for more info.
Wednesday, July 07, 2010
Arteris Adds Support for Tensilica's PIF for Network-on-Chip
This support will make it much easier for designers to get maximum efficiency when integrating Tensilica’s dataplane processing units (DPUs) into their system-on-chip designs. Using Arteris’ NoC technology, Tensilica’s DPUs can be mixed and matched with other processor cores or RTL blocks in complex, high-throughput designs. Tensilica’s DPUs are often used in multi-core chip designs, performing valuable data processing functions such as audio, video and baseband communications.
Wednesday, June 30, 2010
New FLAC Decoder for HiFi Audio DSP Core
FLAC - the Free Lossless Audio Codec - is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. Because it is not a proprietary format, is not encumbered by patents, and has an open-source reference implementation, FLAC has become increasingly popular. More information on FLAC is available at http://flac.sourceforge.net.
Wednesday, June 23, 2010
Eric Clapton Crossroads Concert
Yes, I'm lucky enough to go. So I'll be out of the office, returning Tuesday, 6/28.
Subscribe to:
Posts (Atom)
