Updated White Paper: Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design

Processor buses are increasingly inadequate for high-throughput applications such as video compression/decompression or high-speed networking. A new, configurable feature called "ports and queues," , based on tried-and-true system technology, provides the ASIC and SOC design team with as much bandwidth as any system can possibly use, essentially unlimited I/O bandwidth.

New Job Posting: Senior Baseband DSP SW Engineer, Santa Clara, CA USA

We are looking for a versatile Senior Baseband DSP Software Engineer.  As part of Tensilica's baseband DSP team, you will be responsible for specifying, designing, developing, testing and releasing libraries for baseband communications targeted to a heterogeneous family of baseband DSPs.  The work is carried out both by Tensilica engineers and a network of strategic third party software development partners.  As a result, much of the work will involve detailed technical interaction with these third party software partners, in order to ensure the rapid availability of basic DSP libraries and ported baseband stacks at PHY, MAC and other layers of communication SW targeted to our DSPs.  The work will range from very detailed technical development to external partner relationship development, and you will have a strong influence on the future development of new baseband DSPs at Tensilica.

New white paper: Optimize SOC Performance Using Memory Tuning and System Simulation

Memory tuning lets you choose memory-related parameters for each on-chip processor core to balance system performance, processor area, and memory size by exploring a target application's sensitivity to these memory system issues.

New Job Posting: Sr. Design Verification Engineer - Santa Clara, CA USA

See our entire list of engineering jobs open at our headquarters in Santa Clara and our R&D facility in Pune, India. We're looking for top talent!

EE Journal Reviews Audio IP Cores

The ever increasing complexity of audio software (Tensilica now supports over 80 encoders, decoders and audio-enhancement packages) means that most companies are picking audio-specific IP cores rather than trying to design the cores themselves. Bryon Moyer's overview of audio IP cores does an excellent job of overviewing the complexity involved in audio applications. Read this article, then check out Tensilica's HiFi Audio.

Atheros Introduces New ROCm Chips with Bluetooth, WiFi and GPS for Portable Devices

Atheros Communications, Inc.introduced two new Wi-Fi solutions for cellular phones, tablets, eReaders, gaming devices and other handheld consumer electronic (CE) products. Atheros is raising the performance bar with a 2-stream mobile 802.11n solution for devices that need the higher speed of XSPAN® Wi-Fi capabilities for media applications. Atheros is also delivering the world’s smallest and most energy efficient 1-stream 802.11n solution, which brings the performance and enhanced software features of Align® Wi-Fi to even the sleekest feature phones. You'll find out Xtensa processor inside, of course. 

Huge Crowds View Tensilica's LTE Baseband DSP Demos at MWC in Barcelona

Our booth is full morning to night with appointments and people viewing the demo of our multicore LTE baseband demo. We're streaming a live LTE feed to showcase our capabilities. Stop by our booth in Hall 1, booth 1F39 if you're in Barcelona for MWC.

EETimes Review of ConnX BBE64 Says Tensilica Will Dominate LTE Advanced

This is a great overview of Tensilica's strategy, not just for LTE but for all of our products. We use our own tools, the tools you can license, to generate new products like the ConnX BBE64 for LTE Advanced.

Wolfson Microelectronics Introduces Tensilica-based Audio Chip

The WM0010 is one of the first products of its type on the market to incorporate a low power, high performance Tensilica HiFi DSP core. Working in tandem with the application processor, it combines Wolfson’s low power audio co-processor with embedded system software, algorithms and software support, allowing manufacturers of smartphones, tablet PCs and televisions to integrate their own software components and build an individual HD audio solution that supports an extensive range of key use cases.

mimoOn and Tensilica Demonstrate Atlas LTE Platform for Mobile SDR Baseband at MWC 2011

The demonstration showcases mimoOn's mi!MobilePHY^TM software, a full-featured and certified LTE software solution for user equipment (handsets) that supports mandatory and optional features in the 3GPP Release 8 standard.  With a flexible and scalable architecture, advanced algorithms and roadmap for future 3GPP releases, mimoOn's mi!MobilePHY adds to the already outstanding features and performance of the Tensilica solution.

The Tensilica-based hardware system showcases Atlas LTE downlink functionality, showing end-to-end video content transfer and playback. The demonstration uses Tensilica's ConnX BBE16 DSP (digital signal processor) core, coupled with the newly introduced ConnX SSP16 and ConnX Turbo16 dataplane processors (DPUs) to implement a complete user equipment LTE PHY downlink system. All required functionality is implemented in the Tensilica cores and there is no need for any external hardware blocks, as in other implementations, since Tensilica DPUs are scalable and can range from small, function-specific micro DPUs/DSPs to high-performance DSPs and can be customized to deliver 10x to 100x speed/power improvements.

Tensilica Showcases #1 Position in LTE DSP IP Cores at MWC 2011

Tensilica, Inc. will stand out at this year's Mobile World Congress (MWC) in Barcelona, February 14-18, 2011, as it has moved into the number one position as the supplier of baseband DSP IP cores for the new generation of 4G LTE equipment. Eight of the top 15 LTE chipset manufacturers are working with Tensilica's cores for their designs.

 "Tensilica has jumped to the number one position in baseband DSP IP cores for LTE because they provide the widest range of solutions for mobile handsets and wireless basestations. They've been able to get these products to market quickly by utilizing their customizable DPU technology," stated Will Strauss, president of Forward Concepts and leading DSP analyst. "And the new BBE64 DSP family they're introducing today will be a major step forward to meet the even greater needs of LTE Advanced."

Tensilica's Atlas LTE Reference Architecture DSPs Now Available

The Atlas Reference Architecture uses the Tensilica ConnX BBE16 baseband DSP core coupled with three function-specific dataplane processor cores to allow the baseband PHY SOC developer to create a very low power and minimal size PHY system, while enjoying the flexibility of a fully programmable radio, which is vital for competitive multi-standard user equipment devices (handsets) and femtocells. Atlas supports the 3GPP LTE  standard, as well as other complementary standards such as HSPA+ and WiMAX.

Tensilica Announces ConnX BBE64-128 – the World’s Highest Performance DSP IP Core for LTE Advanced

The ConnX BBE64-128 provides over 100 GigaMACs performance in 28nm high-performance process technology, easily outperforming all other DSP IP cores on the market. The ConnX BBE64-128 was designed to meet the performance requirements for LTE (Long-Term Evolution) Advanced, which required at least five times more processing power than LTE.


Additionally, Tensilica introduced the ConnX BBE64-UE, which is specifically optimized for the low power and small area requirements of LTE Advanced handsets. These two new products are based on the new ConnX BBE64 architecture, which Tensilica's customers can use to optimize a DSP core for their particular requirements. Tensilica's product line also includes DSPs for LTE, including the popular ConnX BBE16 LTE DSP and the new ConnX SSP16, ConnX BSP3, and ConnX Turbo16, also introduced today.

HiSilicon, a Division of Huawei, Extends License of Tensilica’s IP Cores, ConnX Baseband Engine, and HiFi Audio DSP for LTE Base Stations and Handsets

"Now that we've worked for over a year with Tensilica, we are quite impressed with the capabilities, ease of use, and efficiency in terms of power, performance, and area achieved with Tensilica DPUs," stated Teresa He, vice president of HiSilicon.

See Tensilica's Chief Scientist Grant Martin at DesignCon This Afternoon

Grant will be on a panel "Who is the designer of the future?" at 3:45 in Ballroom E at DesignCon today. The panel will discuss issues in the transition from RTL design to a more system's level ESL approach and how that will affect designers. The panel will also discuss whether system-level design methodologies are mature enough to really be widely adopted. Should be a lively discussion.

Great Electronics Weekly Article by David Manners

Read David Manners' comments on the Fujitsu-Tensilica deal.