Speeding Basic DSP Functions - FFT Example Ap Note

This is an introduction and tutorial to techniques applicable to accelerating the radix-2 FFT, using TIE techniques that are simple and easy to implement. This document discusses a basic, but very powerful capability of TIE, the ability to define a register file of any arbitrary width and instructions that perform computations on the register file. Additional techniques, such as FUSION and SIMD, are introduced to show how to further improve performance, along with techniques to reduce gate count. These TIE techniques improve FFT performance by a factor of almost 100 times compared to a conventional processor. While the radix-2 FFT algorithm was chosen to illustrate the use of TIE on a relatively simple DSP algorithm, the techniques covered in this application note apply to accelerating any algorithm.

Tensilica and Iberium Partner for DTV Solutions

"We entered into this partnership because we foresee a need to provide flexible, multi-standard IP solutions for the increasing number and complexity of worldwide DTV standards," stated Slobodan Simovich, Iberium's CEO. "Tensilica's DPU technology is a superior programmable platform that delivers performance and power efficiencies 10 to 100X greater than legacy CPU or DSP platforms."

New Job Post: Sr. Applications Engineer, Santa Clara, CA

Just posted this morning. If you know anyone, we're looking!

Now Hiring: University Program Intern

The University Program Intern is a 10-week summer position aimed at creating a University community that shares information on design projects and updating our University web presence.

RESPONSIBILITIES:
* Evaluate wealth of information we have on over 100 universities that have used Xtensa processors in their research.
* Determine an effective way to present and maintain that information online for (i) maximum interaction between universities and (ii) general industry awareness
* Implement the web presence as part of our existing website (CMS based)
* Determine how best to communicate with universities on a regular basis to maintain interest in our products and facilitate information exchange
Perform other duties as required in this dynamic business.
See our web site for full details. Email resumes to paula@tensilica.com

New Japan Office and Seminar on May 24

Our Japan office is celebrating its move to a larger office by hosting a customer seminar featuring discussions by representatives from NTT DOCOMO and Epson. If you're in Japan, be sure to sign up for our seminar.

Great article: Making IP Tradeoffs for Power

In this interesting article from Chip Design Magazine, the author interviews people from several IP companies, including Tensilica. The key to analyzing hardware design changes is to see what happens to the software once the change is made. That's the beauty of Tensilica's Xenergy tool. Change the processor, test out the software. See what changes make the most sense. Find out more about Xenergy at http://www.tensilica.com/products/literature-docs/application-notes/xtensa-tools/xenergy-energy-optimizator.htm.

Seminar in Japan May 24

Sign up now for our seminar in Yokohama, Japan on May 24. Representatives from NTT DOCOMO and Epson will discuss their use of Tensilica's technology.

Reflections on Cadence Acquisition of Denali

Today Cadence announced that they were acquiring Denali to help fulfill their EDA360 vision. Cadence is far behind Synopsys in providing the entire 360 design view. Way back in the early '90s Synopsys made a huge investment in their DesignWare products, which continues to this day (I was the director of corp. comm at Synopsys from '93-'96).

It's good to see Cadence executing on their vision. Maybe we should expect other acquisitions as well? Who's next?

Whitepaper: Exploiting Core's Law" Geting "More than Moore" productivity from your design

While it is feasible to build ASIC devices with more than 100 million transistors, designing these chips is a big challenge. Programmability vs efficiency trade-offs are examined, and suggestions are made for an improved ASIC design methodology using processors as basic building blocks.

HP LaserJet 1606ND Uses Tensilica's Processor

Following in a grand traditional of HP LaserJet printers based on Xtensa processors, the HP LaserJet 1606DN gets outstanding performance.

New ap note: Using TIE to accelerate Radix-2 FFT

This application note illustrates the acceleration of the radix-2 FFT, using TIE techniques that are simple and easy to implement. This document discusses a basic, but very powerful capability of TIE, the ability to define a register file of any arbitrary width and instructions that perform computations on the register file. Additional techniques, such as FUSION and SIMD, are introduced to show how to further improve performance, along with techniques to reduce gate count.

New Databooks Online

We've posted the databooks for Xtensa 8 and Xtensa LX3 online. Check out the latest features.

New Databooks Online

We've posted the databooks for our Xtensa 8 and Xtensa LX3 processors online now. Come check out the latest features.

Great article: 10 Reasons to Customize a Processor Core

See the article in Electronics Components World. Find out if you should consider customizing a processor core for your application.

New apnote: Using TIE Queues with Xtensa Processors

Want to see how easy it is to use Queues to bypass the bus altogether and get blazing fast data processing through the processor? Read this application note. Where the data is FIFO ordered, like audio samples or network packets, it makes sense to use RTL FIFO queues to manage the physical channel for the data. This note outlines the simple syntax to extend the Xtensa LX processor with input and output FIFO queue interfaces to couple tightly with external RTL FIFO queues

Need Screaming FFT Performance?

Try the ConnX Vectra LX DSP Engine. A basic Tensilica Xtensa LX processor might take 155,389 cycles for a 256pt Radix-4 FFT. But add Vectra LX, and that cycle count drops down to 994. Get performance, just where you need it.