Tensilica and the U.S. Department of Energy’s Lawrence Berkeley National Laboratory today announced a collaboration program to explore new design concepts for energy-efficient high-performance scientific computer systems. The joint effort is focused on novel processor and systems architectures using large numbers of small processor cores, connected together with optimized links, and tuned to the requirements of highly-parallel applications such as climate modeling. These demanding scientific problems require 100 to 1000 times higher computation throughput than today’s high-end computing installations, but conventional systems require so much electricity, generate so much heat, and require such complex physical installations that the costs would be prohibitive. This collaboration in application-directed supercomputing aims at making “exascale systems” (up to 1018 floating point operations per second) feasible and cost-effective.
For more information, see http://www.tensilica.com/news_events/pr_2008_05_05.htm
Tuesday, May 06, 2008
Dolby TrueHD Decoder Added to HiFi 2 Audio Engine
Tensilica, has added the Dolby TrueHD decoder to its audio codec library for Tensilica’s Xtensa HiFi 2 Audio Engine, one of the most popular commercial audio cores for system-on-chip (SOC) designs. Dolby TrueHD is the ultimate high-definition audio experience for next-generation entertainment, delivering warm, realistic and enveloping sound from the Blu-ray Disc format.
For more information, see http://www.tensilica.com/news_events/pr_2008_04_29.htm
For more information, see http://www.tensilica.com/news_events/pr_2008_04_29.htm
Tuesday, April 15, 2008
Free Diamond 106Micro for FPGAs
Tensilica has joined Synplicity’s new ReadyIP Program and is providing the Diamond Standard 106Micro processor core – the industry’s smallest licensable 32-bit processor core based on an industry-standard architecture – free of charge through this program. The ReadyIP program delivers a vendor independent design methodology for FPGA implementation and allows designers to easily access, evaluate and incorporate third-party intellectual property (IP), like the Diamond Standard 106Micro, using Synplicity’s Synplify Pro and/or Synplify Premier Version 9.2 FPGA synthesis environments.
This week at the Embedded Systems Conference (ESC) in San Jose, CA, the companies will showcase how easy it is to download Tensilica’s Diamond Standard 106Micro processor core through the Synplicity tool flow.
For more information, see http://www.tensilica.com/news_events/pr_2008_04_15.htm
This week at the Embedded Systems Conference (ESC) in San Jose, CA, the companies will showcase how easy it is to download Tensilica’s Diamond Standard 106Micro processor core through the Synplicity tool flow.
For more information, see http://www.tensilica.com/news_events/pr_2008_04_15.htm
Thursday, April 03, 2008
Chris Rowen Elected to EDA Consortium Board of Directors
Chris Rowen, president and CEO of Tensilica, Inc., was elected to the Board of Directors of the EDA Consortium, the international association of companies developing EDA tools and services that enable engineers to create the world's electronic products.
“The EDA Consortium is ideally positioned in two key areas,” Rowen stated. “First, it’s positioned to raise the profile of EDA’s special role among customers, investors, developers, the electronics media and the broader public. Second, it plays an important role coordinating computing platform strategies, influencing export license models, pressing for smart education and immigration policies, and other key industry concerns. I am excited about serving this important community.”
Dr. Chris Rowen was a pioneer in the development of RISC architecture at Stanford in the early 1980s and helped start MIPS Computer Systems Inc. in 1984, where he served in a variety of functions including vice president for Microprocessor Development and managed MIPS in Europe. When Silicon Graphics purchased MIPS, he became the technology and market development leader for Silicon Graphics Europe. In 1996, he became Synopsys’ vice president and general manager of the Design Reuse Group. He founded Tensilica in July 1997. He received a B.A. in physics from Harvard University and M.S. and Ph.D. in electrical engineering from Stanford University.
“The EDA Consortium is ideally positioned in two key areas,” Rowen stated. “First, it’s positioned to raise the profile of EDA’s special role among customers, investors, developers, the electronics media and the broader public. Second, it plays an important role coordinating computing platform strategies, influencing export license models, pressing for smart education and immigration policies, and other key industry concerns. I am excited about serving this important community.”
Dr. Chris Rowen was a pioneer in the development of RISC architecture at Stanford in the early 1980s and helped start MIPS Computer Systems Inc. in 1984, where he served in a variety of functions including vice president for Microprocessor Development and managed MIPS in Europe. When Silicon Graphics purchased MIPS, he became the technology and market development leader for Silicon Graphics Europe. In 1996, he became Synopsys’ vice president and general manager of the Design Reuse Group. He founded Tensilica in July 1997. He received a B.A. in physics from Harvard University and M.S. and Ph.D. in electrical engineering from Stanford University.
Tuesday, April 01, 2008
New GUI Helps Cut Chip Energy Consumption
Tensilica has added a new graphical user interface (GUI) to its popular Xenergy estimator, a unique energy estimator for both Xtensa configurable processors and Diamond Standard processors. This “first of its kind” tool allows software developers to evaluate trade-offs, so their software can be optimized for power, and lets hardware designers optimize the design of Xtensa configurable processors for total energy consumption. For more information, see http://www.tensilica.com/news_events/pr_2008_03_31.htm
Tuesday, March 25, 2008
VaST Models Support Electronics Virtualization for Consumer Electronics OEMs
Models of Tensilica processors are now available from VaST Systems for the VaST CoMET System Engineering Environment.
Xtensa and Diamond Standard processor designers will be able to easily import the cycle accurate instruction set simulator provided by Tensilica into the VaST platform for early architectural exploration and software development and debugging. Chip designers can test their Tensilica processor-based designs early in the design cycle with real software using VaST virtual system prototypes, significantly shortening the overall design cycle compared to traditional design methods and allowing designers to test design trade-offs while changes can still be cost-effectively made.
For more information, see http://www.tensilica.com/news_events/pr_2008_03_25.htm
Xtensa and Diamond Standard processor designers will be able to easily import the cycle accurate instruction set simulator provided by Tensilica into the VaST platform for early architectural exploration and software development and debugging. Chip designers can test their Tensilica processor-based designs early in the design cycle with real software using VaST virtual system prototypes, significantly shortening the overall design cycle compared to traditional design methods and allowing designers to test design trade-offs while changes can still be cost-effectively made.
For more information, see http://www.tensilica.com/news_events/pr_2008_03_25.htm
Wednesday, March 12, 2008
Xtensa Processors Enable Next-Generation Mobile HD Radio Technology
Tensilica's Xtensa configurable processor has been designed into the baseband processor in Samsung EM’s HD Radio chipset. The baseband processor, based on a design by iBiquity Digital Corporation, the developer and licensor of HD Radio technology and a Tensilica processor reseller, integrates the memory, SDRAM and flash in a system-in-package measuring just 9 x 9 mm. Including the companion RF (radio frequency) chip, this low-power chip set’s total power consumption is 150 mW, making it ideal for a wide range of battery powered portable devices capable of tuning and demodulating AM/FM radio broadcast in both analog and HD Radio digital technology.
For more information, see http://www.tensilica.com/news_events/pr_2008_03_11.htm
For more information, see http://www.tensilica.com/news_events/pr_2008_03_11.htm
Tuesday, March 04, 2008
Cisco Announces 40-core Quantumflow Router
From EETimes:
Cisco Systems debuts Tuesday (March 4) a router that packs on a custom 40-core processor a wide variety of networking services. The Ethernet giant aims to leverage its expertise designing complex ASICs to leapfrog competition in the $5 billion market for edge routers.
The Quantum Flow Processor takes to a new level Cisco's work on ASICs for its networking systems, surpassing in some ways technology in mainstream server CPUs from Intel Corp. and Sun Microsystems.
Key to the system is the 1.3 billion transistor flow processor, an 80W chip made in a 90nm process at Texas Instruments and designed using Cisco's customer-owned tooling. Each of its 40 Tensilica cores can handle up to four threads, far beyond the raw thread-level parallelism of Sun's 65nm Niagara or Intel's 45nm Penryn server CPUs.
See the entire article at http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=T0ZYZJXI22R0MQSNDLSCKHA?articleID=206901479
Cisco Systems debuts Tuesday (March 4) a router that packs on a custom 40-core processor a wide variety of networking services. The Ethernet giant aims to leverage its expertise designing complex ASICs to leapfrog competition in the $5 billion market for edge routers.
The Quantum Flow Processor takes to a new level Cisco's work on ASICs for its networking systems, surpassing in some ways technology in mainstream server CPUs from Intel Corp. and Sun Microsystems.
Key to the system is the 1.3 billion transistor flow processor, an 80W chip made in a 90nm process at Texas Instruments and designed using Cisco's customer-owned tooling. Each of its 40 Tensilica cores can handle up to four threads, far beyond the raw thread-level parallelism of Sun's 65nm Niagara or Intel's 45nm Penryn server CPUs.
See the entire article at http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=T0ZYZJXI22R0MQSNDLSCKHA?articleID=206901479
Monday, March 03, 2008
Tensilica and NuFront Show T-MMB Mobile TV Solution at China’s IIC 2008 Shows
Tensilica and NuFront will jointly exhibit at the IIC-China 2008 exhibitions March 3-4, 2008, in Shenzhen (booth:2K41) and March 10-11, 2008, in Shanghai (booth:4S41). Using Tensilica’s configurable processor technology, NuFront developed, and has gone into mass production with, a T-MMB (terrestrial-mobile multimedia broadcasting) mobile baseband DSP (digital signal processor). By watching mobile TV on a T-MMB phone, visitors will be able to experience NuFront’s technology in action.
The T-MMB mobile TV standard is in the running to be adopted throughout China, and there are plans to have this in place in time for the Beijing Olympics.
NuFront’s T-MMB mobile TV baseband chip employs Tensilica’s Xtensa® configurable processor. "Tensilica’s Xtensa processor was very attractive for our next design because standard processor cores couldn’t give us the performance we needed,” stated Hamilton Yong, COO, NuFront Software. “The only way to get the performance was to optimize the processor, and Tensilica is the only company with the automated tools to make that customization much easier and ensure our success.”
The T-MMB mobile TV standard is in the running to be adopted throughout China, and there are plans to have this in place in time for the Beijing Olympics.
NuFront’s T-MMB mobile TV baseband chip employs Tensilica’s Xtensa® configurable processor. "Tensilica’s Xtensa processor was very attractive for our next design because standard processor cores couldn’t give us the performance we needed,” stated Hamilton Yong, COO, NuFront Software. “The only way to get the performance was to optimize the processor, and Tensilica is the only company with the automated tools to make that customization much easier and ensure our success.”
WiLinx Licenses Tensilica’s Xtensa LX2 Processor Core For Low-Power UWB Chips
WiLinx licensed the Xtensa LX2 configurable processor for its low-power True-UWB single chip CMOS (Complementary Metal-Oxide-Semiconductor) solutions. WiLinx True-UWB product offers 7 GHZ (from 3 to 10 GHz) of air spectrum as the key enabler for worldwide adoption of UWB into the cellular phone handsets, PCs, PC peripherals and CE (consumer electronics) devices.
“Following an in-depth technical analysis, we selected Tensilica’s Xtensa LX2 configurable processor core for our single chip low power True-UWB product families. The 7-GHz coverage of our solution unleashes the full capacities of the WiMedia based UWB solution to our customers. In particular it includes ‘above 6 GHz WiMedia bands,’ mandatory for Bluetooth-3.0 enabled devices,” stated Masoud Djafari, CEO and co-founder of WiLinx. “Tensilica’s easily configurable processor technology plays a key role in delivering the feature rich WiMedia protocol at low power and cost. It also makes the product more flexible for future upgrades.”
For more information:
“Following an in-depth technical analysis, we selected Tensilica’s Xtensa LX2 configurable processor core for our single chip low power True-UWB product families. The 7-GHz coverage of our solution unleashes the full capacities of the WiMedia based UWB solution to our customers. In particular it includes ‘above 6 GHz WiMedia bands,’ mandatory for Bluetooth-3.0 enabled devices,” stated Masoud Djafari, CEO and co-founder of WiLinx. “Tensilica’s easily configurable processor technology plays a key role in delivering the feature rich WiMedia protocol at low power and cost. It also makes the product more flexible for future upgrades.”
For more information:
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