Everything You Wanted to Know About Blu-ray Audio

Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.
http://tinyurl.com/yc9ekeq

The Fastest DSP Core Tested by BDTI

See BDTI's report on Xtensa LX - the fastest DSP core BDTI has ever tested. http://www.tensilica.com/uploads/pdf/BDTI-tensilica_wp-1.pdf

Apnote: Fast Interrupt Handling

Fast interrupt handling is important to system throughput and responsiveness. This application note describes a method to use existing Xtensa features and configuration options to support very fast interrupt handling. This note focuses on the interrupt handling case, i.e, that case where one task is running, but is preempted at some random point by an external or timer interrupt, which then performs an independent task. See http://www.tensilica.com/products/literature-docs/application-notes/system-software/interrupt-handling.htm

White Paper: Get Your ASICs and SOCs Off the Bus!

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.

http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/

Whitepaper: 10 Tips for Successful SOC Design

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design. See http://www.tensilica.com/products/literature-docs/white-papers/10-tips-for-soc-design/

2pm PT today (Wed) - See Grant Martin at SOC Online Conference

EETimes SOC online conference today - see 2pm discussion: Economics of Next-Generation SoC Design: A node too far? with Tensilica Chief Scientist Grant Martin. More info at http://tinyurl.com/lrhr6l Don't miss it!

Have You Checked the Processor and DSP Checklist?

SOC designs are major, high-risk projects and most consist of many IP blocks-some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and EDA flow scripts, these processor IP blocks can literally make or break your project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. http://www.tensilica.com/products/literature-docs/white-papers/ia-processor-dsp-ia-processor-and-dsp-iip-selection-checklist.htm

New ConnX Baseband Engine Product Brief

See what a DSP with 16 18-bit MACs/cycle can do for you. Perfect for next-gen baseband radios and receivers. Hot off the press (or at least newly posted to the web site). http://www.tensilica.com/uploads/pdf/connx_bbe.pdf

Sign Up Now For EETimes SOC Online Conference Wed 9/16

Tensilica's Chief Scientist Grant Martin will participate in panel at 5 pm Eastern Time: Economics of Next-Generation SoC Design: A node too far?

The cost of both design and manufacturing is growing exponentially at each new technology node. The largest chip companies will continue to push scaling forward for the foreseeable future. But what about the rest of the field? At what point does it stop making sense for companies to move to the next node? To what degree is this a function of design and/or verification costs? In what application areas does it make sense for companies to deploy FPGA-based SoC designs. This panel will examine the state of the economics of different forms of SoC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon.

See the entire schedule and sign up now: http://www.eetimes.com/soc/program_schedule/;jsessionid=1UQ1JNW4L3TCPQE1GHPSKH4ATMY32JVN

It's what they don't tell you about power specs that matter.

Anyone familiar with board-level design has developed an intuitive feel for packaged-processor power specifications: the processor draws a certain amount of power, give or take a percentage based on process variation and speed binning. For a variety of reasons, this intuition utterly fails with respect to vendor specifications for processor core IP. Read our white paper: Processor Core Power Specs: A Cautionary Tale at http://www.tensilica.com/products/literature-docs/white-papers/power-specs/

Have You Seen the Video?

See how easy it is to configure an Xtensa processor with just the options you need. Tensilica's CTO Chris Rowen leads you through an actual example. http://www.tensilica.com/products/xtensa-customizable/configurable.htm

Read Microprocessor Report's review of ConnX Baseband Engine

Every "radio" in notebooks, netbooks, smartphones, mobile Internet devices, WiMAX, DTV, digital radio and more - with a chip-scale wireless transmit/receive unit - needs a baseband processor. See what Microprocess Report had to say about Tensilica's Baseband Engine. http://www.tensilica.com/uploads/pdf/MR_baseband_0809.pdf

Back from vacation - now back to work

Just spent a very nice week in South Lake Tahoe - we're so lucky in California to have wonderful places to drive to for vacation. Now I'm back and getting into the swing of things here at Tensilica. We're going to have a busy fall.