Read Microprocessor Report's "Tensilica DSP Targets LTE Advanced"

Microprocessor Report has concluded an extensive review of Tensilica's ConnX BBE64 DSP. They conclude: Designers seeking an alternative to principally hardwired baseband designs in order to accelerate time to market, keep algorithm development in the software domain, or achieve flexibility will thus find the BBE64 a capable processor for next-generation basebands in cellular modems, handsets, and base stations.

New White Paper: Seven Critical Questions to Ask When Selecting a Digital Audio Solution for Your Next Mobile SOC Design

The complexity of delivering a mobile audio IP solution to SOC designers causes design teams to ask many, many questions before choosing an audio core and associated codecs. That's a good thing. The selection process is complex, and the more information you have before making the decision, the better. Experience shows that design teams' questions about mobile audio solutions fall into seven broad categories. Read more about it in our white paper.

EETimes Review of New Xtensa LX4 Core

Read EETimes online coverage of the new Xtensa LX4 core, titled, "Tensilica adds DSP in cellular battle," with analysis and quotes from Will Strauss, noted DSP analyst.

Introducing Xtensa LX4 - with 4X the Data Bandwidth for High-Performance DSP

Xtensa LX4 is ideal forcompute-intensive dataplane and DSP functions such as imaging, video, networking and baseband wired/wireless communications. Any application that requires extensive data processing will significantly benefit from the breakthrough features - particularly those that quadruple data bandwidth -  built into Tensilica's new Xtensa LX4 dataplane processor (DPU) for SOCs
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The new Xtensa LX4 DPU supports wider local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option that boosts overall performance for systems with long off-chip memory latency. Tensilica is already using many of these capabilities in its recently introduced ConnX BBE64 DSP for LTE Advanced communications.

Tensilica's Grant Martin in Today's EETimes Multicore Virtual Conference

At 2 pm Pacific Time today. Multicore processors are forcing a rethink of hardware design as well as programming practices. Do you want multiple identical CPU cores or a mix of difference CPU cores for each task? What's the best way to harness all this horsepower? And do multicore chips really reduce power consumption or are they just performance overkill? Whatever the answers, multicore isn't going away. It's a design reality. Whether you're an engineer, a manager, or a programmer, a few intensive hours spent here will pay off now and down the road. See Tensilica's Chief Scientist Grant Martin address these and other questions.

New White Paper: 7 Critical Questions to Ask When Selecting a Digital Audio Solution for SOC Design

The complexity of delivering a mobile audio IP solution to SOC designers causes design teams to ask many, many questions before choosing an audio core and associated codecs. That's a good thing. The selection process is complex, and the more information you have before making the decision, the better. Experience shows that design teams' questions about mobile audio solutions fall into seven broad categories. Read this white paper to find out more.

Updated white paper: Everything you wanted to know about SOC memory, but were afraid to ask

If you are a member of an SOC design team, or if you manage one, then memory is critically important to you. On today's multicore SOC designs, more on-chip silicon is devoted to memory than to anything else on the chip and yet memory is often added as an afterthought. Don't let that happen to your team.

Audio DSP, Baseband DSP, or Your Own Customized Value-Add Engine – Tensilica’s IP Cores Excel in the SOC Dataplane

Tensilica is the #1 supplier of audio DSP IP cores and 4G baseband DSP IP cores for the mobile, handset, and home entertainment markets. In fact, no matter what the function is, if your SOC design demands a highly-efficient, programmable computational engine for a data-intensive task, our innovative technology can provide a solution for you.
    For the most common and broadly applicable tasks in the dataplane, Tensilica has ready made solutions like our HiFi Audio DSPs, our ConnX Communications DSPs and our Diamond Standard controllers for deeply embedded dataplane control.
    For more specialized tasks, you can rapidly build your own customized dataplane processor for tasks like image signal processing, video processing, security protocol processing, or network packet processing using our Xtensa Processor Generator.

Sending Good Thoughts to Everyone in Japan

It's so horrifying to see the TV footage coming in from Japan after the earthquake, tsunami and fires. Our employees in our Yokohama office were fine, but the office had to be evacuated and everyone had to get home, which is not easy under the best circumstances in Japan. Our thoughts are with everyone there.

New white paper: Avoid Bus Bottlenecks

Think the only way to get data into and out of a processor is through the bus. Think again. Tensilica offers innovative I/O that lets you stream data through the processor, never touching that main bus. This white paper explains how you can avoid bus bottlenecks and increase performance by using this innovative I/O, providing RTL-like data flows.