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Monday, September 22, 2008

Triductor Licenses Tensilica Diamond Standard 212GP Processor Core

Triductor Technology, of Santa Clara, CA, and Suzhou, China, has signed a second license for the Diamond Standard 212GP general-purpose processor core and has completed a second design tape out. Triductor has used the Diamond 212GP processor as the system controller for VDSL2 design for both the customer premise (CPE) and central office (CO) designs. The Diamond 212GP is an area-efficient, low-power, fully synthesizable 32-bit RISC processor core that also supports basic single-MAC DSP functions. Read more at http://www.tensilica.com/news_events/pr_2008_07_08.htm

Friday, June 06, 2008

Imperas Announces Licensing, Distribution Relationship with Tensilica

Tensilica has signed a partnership agreement with Imperas to allow fast functional, instruction accurate models of its popular Xtensa and Diamond Standard processors to run on Open Virtual Platform (OVP) based virtual platforms. Specifically, wrapper files enabling integration of the Tensilica processor models are now available for free download from the OVPworld.org website. These models will run with Tensilica’s TurboXim fast functional simulator, which simulates at speeds 40 to 80 times faster than a traditional instruction set simulator.

For more information, see http://www.tensilica.com/news_events/pr_2008_06_06.htm

Tensilica and SPIRIT DSP Partner for Mobile Multimedia Audio and Voice

SPIRIT DSP, the world’s leading supplier of voice, audio and video software engines, and Tensilica, Inc. today announced that they have formed a strategic partnership and can now deliver 18 optimized, high quality digital audio and voice software packages that run on Tensilica’s HiFi 2 Audio Engine, an increasingly popular audio architecture for system-on-chip (SOC) designs.

Immediately available, SPIRIT audio software packages include: AAC-LC decode and encode, aacPlus v1 and v2 decode and encode, BSAC decode, MP3 decode and encode, Ogg Vorbis decode, and WMA decode and encode. Voice codecs include AMR-NB (narrowband), AMR-WB and G.729AB.

For more information, see http://www.tensilica.com/news_events/pr_2008_06_04.htm

New Open Source Linux Program

Tensilica, Inc. today announced that Embedded Linux 2.6 and GNU tools based on GCC 4.2, both available at www.linux-xtensa.org, is now backed by two well-respected Linux industry partners.

Embedded Alley Solutions, Inc. of San Jose, CA, provides Platform Optimized Linux Solutions, Linux consulting services and training. Timesys, of Pittsburgh, PA, is providing subscriptions to LinuxLink for Tensilica customers to access embedded software, tools, documentation, and support and Timestorm: an Eclipse-based IDE that provides a point-and-click interface for kernel and root filesystem configuration, profiling, testing, and debugging.

Read more at http://www.tensilica.com/news_events/pr_2008_06_02.htm

Tuesday, May 06, 2008

Lawrence Berkeley National Laboratory and Tensilica Collaborate

Tensilica and the U.S. Department of Energy’s Lawrence Berkeley National Laboratory today announced a collaboration program to explore new design concepts for energy-efficient high-performance scientific computer systems. The joint effort is focused on novel processor and systems architectures using large numbers of small processor cores, connected together with optimized links, and tuned to the requirements of highly-parallel applications such as climate modeling. These demanding scientific problems require 100 to 1000 times higher computation throughput than today’s high-end computing installations, but conventional systems require so much electricity, generate so much heat, and require such complex physical installations that the costs would be prohibitive. This collaboration in application-directed supercomputing aims at making “exascale systems” (up to 1018 floating point operations per second) feasible and cost-effective.
For more information, see http://www.tensilica.com/news_events/pr_2008_05_05.htm

Dolby TrueHD Decoder Added to HiFi 2 Audio Engine

Tensilica, has added the Dolby TrueHD decoder to its audio codec library for Tensilica’s Xtensa HiFi 2 Audio Engine, one of the most popular commercial audio cores for system-on-chip (SOC) designs. Dolby TrueHD is the ultimate high-definition audio experience for next-generation entertainment, delivering warm, realistic and enveloping sound from the Blu-ray Disc format.

For more information, see http://www.tensilica.com/news_events/pr_2008_04_29.htm

Tuesday, April 15, 2008

Free Diamond 106Micro for FPGAs

Tensilica has joined Synplicity’s new ReadyIP Program and is providing the Diamond Standard 106Micro processor core – the industry’s smallest licensable 32-bit processor core based on an industry-standard architecture – free of charge through this program. The ReadyIP program delivers a vendor independent design methodology for FPGA implementation and allows designers to easily access, evaluate and incorporate third-party intellectual property (IP), like the Diamond Standard 106Micro, using Synplicity’s Synplify Pro and/or Synplify Premier Version 9.2 FPGA synthesis environments.

This week at the Embedded Systems Conference (ESC) in San Jose, CA, the companies will showcase how easy it is to download Tensilica’s Diamond Standard 106Micro processor core through the Synplicity tool flow.

For more information, see http://www.tensilica.com/news_events/pr_2008_04_15.htm

Thursday, April 03, 2008

Chris Rowen Elected to EDA Consortium Board of Directors

Chris Rowen, president and CEO of Tensilica, Inc., was elected to the Board of Directors of the EDA Consortium, the international association of companies developing EDA tools and services that enable engineers to create the world's electronic products.

“The EDA Consortium is ideally positioned in two key areas,” Rowen stated. “First, it’s positioned to raise the profile of EDA’s special role among customers, investors, developers, the electronics media and the broader public. Second, it plays an important role coordinating computing platform strategies, influencing export license models, pressing for smart education and immigration policies, and other key industry concerns. I am excited about serving this important community.”

Dr. Chris Rowen was a pioneer in the development of RISC architecture at Stanford in the early 1980s and helped start MIPS Computer Systems Inc. in 1984, where he served in a variety of functions including vice president for Microprocessor Development and managed MIPS in Europe. When Silicon Graphics purchased MIPS, he became the technology and market development leader for Silicon Graphics Europe. In 1996, he became Synopsys’ vice president and general manager of the Design Reuse Group. He founded Tensilica in July 1997. He received a B.A. in physics from Harvard University and M.S. and Ph.D. in electrical engineering from Stanford University.

Tuesday, April 01, 2008

New GUI Helps Cut Chip Energy Consumption

Tensilica has added a new graphical user interface (GUI) to its popular Xenergy estimator, a unique energy estimator for both Xtensa configurable processors and Diamond Standard processors. This “first of its kind” tool allows software developers to evaluate trade-offs, so their software can be optimized for power, and lets hardware designers optimize the design of Xtensa configurable processors for total energy consumption. For more information, see http://www.tensilica.com/news_events/pr_2008_03_31.htm

Tuesday, March 25, 2008

VaST Models Support Electronics Virtualization for Consumer Electronics OEMs

Models of Tensilica processors are now available from VaST Systems for the VaST CoMET System Engineering Environment.

Xtensa and Diamond Standard processor designers will be able to easily import the cycle accurate instruction set simulator provided by Tensilica into the VaST platform for early architectural exploration and software development and debugging. Chip designers can test their Tensilica processor-based designs early in the design cycle with real software using VaST virtual system prototypes, significantly shortening the overall design cycle compared to traditional design methods and allowing designers to test design trade-offs while changes can still be cost-effectively made.

For more information, see http://www.tensilica.com/news_events/pr_2008_03_25.htm