Amazon Kindle - Tensilica Inside

Yes, Tensilica's inside the WiFi chip in the new WiFi-enabled, slimmer Amazon Kindle.

Over 150 Companies Design with Tensillica Cores

Who are Tensilica's customers? Click on the headline to find out. We have over 150 companies that have used Tensilica's cores in their chip designs. Some won't let us list their name, but the list still is very impressive.

D-Link's new Boxee Box based on Tensilica Audio

This innovative Intel-based box gives you Internet freedom on your TV. The Boxee Box lets you choose the TV shows you want to watch and the ones you want to pay for. No cable service necessary. It includes an incredible selection of movies in HD, as well as over 40,000 TV episodes from your favorite networks.

Fujitsu invest in Tensilica

“After working with Tensilica on the development of advanced performance on our mobile terminals we realized how important Tensilica’s DPU foundation has become to our engineers,” stated Minoru Sakata, President, Mobile Phones Unit, Fujitsu Limited. “Tensilica’s customizable DPUs help us get maximum performance with the lowest possible power in high throughput, signal processing-intensive mobile wireless devices.”

With Customizable Processors, You can Lower Power - Significantly

In fact, customized Xtensa DPUs can even rival the power efficiency of dedicated RTL blocks thanks to advanced, automated power minimization features auto-generated by the Xtensa Processor Generator that must be manually implemented in a custom RTL block design.

Use Customizable Processors as Basic SOC Building Blocks

Now there’s a real alternative to RTL design. You can use customizable Xtensa processors to finish your design much faster and add flexibility to adapt to changing standards or product requirements. Tensilica’s Xtensa processors provide both the I/O throughput and the computational performance previously only available with RTL design. The generated processor fully rivals the performance and efficiency of hand-coded RTL blocks with many concurrent operations, efficient data types and optimized multiple wide deep pipelines. Read this 5-page section for more information.

AppliedMicro Picks Tensilica for High-Throughput Comms Chip Design

"We selected Tensilica's DPUs because of their remarkable ability to be customized with high-bandwidth, efficient interfaces, such as FIFO-like queues, to quickly stream data into and out of the processor," stated Sean Campeau, AppliedMicro's senior manager of engineering. "These high-speed connections bypass the main system bus altogether, allowing us to implement functions in the processor that previously could only meet our performance targets by being implemented in RTL (register transfer level) logic. Implementing these functions in a processor speeds our design effort considerably and gives us a much more flexible solution."

Why Highest MHz Does Not Mean Highest Performance

Read this white paper to see how you can boost SOC performance without driving clock rates and power dissipation through the roof.

Why Not Use Processors in the SOC Dataplane?

Tensilica offers the core technology that overcomes the top four objections to using processors in the dataplane:
1. Data throughput - Tensilica allows designers to bypass the main system bus, just like a block of RTL.
2. Fit into hardware design flow - We provide glueless pin-level co-simulation of the ISS with Verilog simulators from the leading EDA companies.
3. Processing speed - Customization yields speeds 10 to 100 times that of traditional processors and DSPs.
4. Customization challenges - Our process is automated - you can't break our cores!

Need a ultra high performance 32-bit core? Look at the Diamond 570T

With a Dhrystone 2.1 rating of 1.59 DMPIS/MHz, the Diamond Standard 570T is powered by dual 32x32 SIMD MULs and a 32-bit integer divider. It has built-in 16-bit DSP instructions plus high-speed interfaces. Oh my, what a controller!