Tensilica Picks EVE's ZeBu for Validation of Diamond Video Core

Tensilica used EVE’s ZeBu to validate the Diamond 38xVDO Video Engines. Targeted at mobile handsets and personal media players (PMPs), Tensilica’s Diamond Standard Video Engines are fully programmable to support VGA and standard definition (SD, also known as D1) video codecs.

ZeBu (for Zero Bugs) gives Tensilica verification engineers an easy-to-use and affordable solution that combines the best aspects of traditional emulation and rapid prototyping systems. It is used in Tensilica’s system-level regression testing, hardware/software integration, application and codec development, conformance testing and profiling. ZeBu also proved useful in validating multi-processor synchronous debugging. In addition to allowing software engineers to validate codecs, ZeBu also helped Tensilica’s engineers find subtle bugs during product development related to clock tree issues missed during register transfer level (RTL) simulation.

For more information, see http://www.tensilica.com/news_events/pr_2007_09_18.htm

Tensilica Joins Chip Estimate's Prime IP Partner Program

As a Prime IP Partner, Tensilica is enabling centralized access to information about the company’s standard processor cores and configurable processor technology at ChipEstimate.com. Tensilica IP solutions for system-on-chip (SOC) designs allow designers to create lower power, higher performance hardware and software for their integrated circuits.

ChipEstimate.com was launched in 2005 to provide comprehensive chip planning capabilities to the electronics and semiconductor community. In addition to the comprehensive IP catalog, designers can use the InCyte software available through the website to plan their next chips and explore die size, power, leakage and cost tradeoffs. Tensilica IP can now be searched for and considered in chip estimations though the portal.

A complete list of Chip Estimate IP partners can be seen at http://www.chipestimate.com/vendorlist.php.

P-Product Ports Codecs to the HiFi 2 Audio Engine

“Customers interested in custom ports of specialized audio codecs can turn to P-Product because they have the expertise in programming Tensilica's HiFi 2 Audio Engine platform,” stated Larry Przywara, Tensilica's director of mobile multimedia. “With their porting and algorithm optimization experience, P-Product is a strong asset for our HiFi 2 customers.”

“The HiFi 2 Audio Engine is a very well optimized core for all audio functions, ranging from low-power MP3 to high-end surround sound,” stated Michael Vulikh, CEO of P-Product. “The audio centric instructions Tensilica created enable easy programming in C code, avoiding the time consuming assembly-level programming usually required when porting audio algorithms to the typical DSPs and CPUs. The HiFi2 audio engine allows us to deliver superior MHz performance with far less development effort.”

P-Product has already ported audio software to Tensilica's HiFi 2 Audio Engine and has significant expertise in audio and video software porting.

Webcast this Wednesday

Tensilica will present a live webcast, “Using Configurable Processors as Enhanced
Application Processors and Controllers,” highlighting the way for SOC (system on chip) designers to achieve high performance while keeping the processor core area very small. The seminar will show the process of evaluating code for hot spots and then accelerlerating those functions using configuration options and the Verilog-like Tensilica Instruction Extension (TIE) language.

This webcast is Wednesday, September 12, at 11:00 a.m. PT / 2 p.m. ET. Sign up here: https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&eventid=92084&sessionid=1&key=477F1AD28B50C3D5E0FA6677040660D1&partnerref=sponlink&sourcepage=register

Tensilica and Tallika Announce Secure SOC FPGA Platform

The Configurable Secure SOC FPGA/ASIC Platform, based on Tensilica’s Xtensa Processor, is a fully verified and silicon proven hardware/software platform that is ideal for any design team that needs a full implementation of RSA (including encryption, decryption, and key-pair generation acceleration) and/or an SOC with integrated hardware security functions.
Tallika’s security solution includes a 32-bit AHB/APB backbone and Tallika’s linked-list-based DMA controller integrated with its security IP blocks - AES/TDES/SHA/MD5 on the AHB bus and 2048-bit native exponentiation engine on the APB bus. The Secure FPGA Platform is based on Xilinx Virtex4 LX160 FPGA devices and comes with a complete software library to access security functions as well as with a full implementation of RSA encrypt, decrypt, and key-pair generation (including acceleration for Primality testing). The solution is also available for license by Tallika as soft IP for ASIC development.

The Secure Platform core IP and FPGA platform are available now from Tallika. More information regarding this solution can be found at http://www.tallika.com/products_security_secure_soc.htm.