Virage Logic 's Core-Optimized IP Kits

Tensilica Inc. and Virage Logic introduced sixteen specially designed Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family members for manufacture on TSMC’s 130-nanometer (nm) and 90nm G processes. The new Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) ASAP Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores to allow designers to target area, performance or power. For more information, see http://www.tensilica.com/news_events/pr_2006_12_11.htm