Diamond Standard Processors Named to EDN’s Hot 100 Products of 2006

EDN Magazine (www.ednmag.com) named the Tensilica Diamond Standard Processor family to its list of Hot 100 Products of 2006.

According to EDN, “Built by and for electronics engineers, this list distills the most innovative and significant products of the year, including process technologies, power sources, processor cores, communication controllers, test instruments, embedded boards, EDA tools, and more.

“Our editors mercilessly cull the herd of new-product announcements they see during the year, resulting in this distillation of the most innovative and significant offerings,” EDN added.

EDN’s Top 100 list can be viewed at http://www.edn.com/article/CA6399100.html.

Wirpo is Tensilica's Newest Design Center Partner

Wipro Technologies, the global IT Services arm of Wipro Limited (NYSE:WIT), is Tensilica’s newest processor core design center partner. As a Tensilica design center and Tensilica Xtensions Network partner, Wipro will combine its extensive intellectual property (IP) portfolio, systems knowledge, architecture modeling and verification expertise with system-on-chip (SOC) design services for customers using Tensilica’s Xtensa configurable processors or Diamond Standard processor cores.

Madhu Parthasarathy, general manager, DSP & Multimedia Applications, Wipro Technologies, said, “Our advanced algorithm group has been actively evaluating processors to address the low-cost, enhanced computing requirements of applications in the biometric space, such as fingerprint recognition/matching. The Tensilica Diamond processor series meet the requirements and also offers the added advantage of a logically scalable path to extend our algorithms to a wider range of applications that our HW-SW architecture group and the HW acceleration service lines view as essential to cater to the complex SOC requirements in the future.”

Virage Logic 's Core-Optimized IP Kits

Tensilica Inc. and Virage Logic introduced sixteen specially designed Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family members for manufacture on TSMC’s 130-nanometer (nm) and 90nm G processes. The new Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) ASAP Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores to allow designers to target area, performance or power. For more information, see http://www.tensilica.com/news_events/pr_2006_12_11.htm

Tensilica Introduces Four Video Processor Engines Including Main Profile H.264 Support

Tensilica introduced four new Diamond Standard VDO (ViDeO) processor engines customized for multi-standard, multi-resolution video. Targeted at mobile handsets and personal media players (PMPs), these video subsystems are fully programmable to support all popular VGA and standard definition (SD, also known as D1) video codecs with resolutions up to 720x480 (NTSC) and 720x576 (PAL) including H.264 Main Profile, VC-1 Main Profile, MPEG-4 Advanced Simple Profile (ASP), and MPEG-2 Main Profile, each of which is available from Tensilica. Lower resolutions such as QCIF, QVGA, CIF and VGA are also supported.

The Diamond Standard VDO engines host all the key video processing functions in software on the cores – including the network abstraction layer, picture layer, slice layer, bit-stream parsing and entropy decoding and encoding. This includes the computationally demanding CABAC (Context Adaptive Binary Arithmetic Coding) decoding in the H.264 Main profile decoder that most other solutions omit, implement in a separate and complex non-programmable hardware block or necessitate more than 700 MHz of general CPU workload which significantly increases power consumption. By implementing CABAC in instruction set extensions, Tensilica was able to create a low MHz and power efficient version of CABAC in less than half the area of a typical CABAC hardware block.

The Diamond VDO family offers both Baseline and Main profile solutions – Main profile offers superior data compression and video quality and is the preferred coding scheme at resolutions of D1 and higher for advanced handset and PMP applications. Most other video solutions for SOC design only implement Baseline profile video.

Next Generation Xtensa Configurable Processors

On December 4, Tensilcia introduced its next-generation Xtensa configurable processors, the Xtensa LX2 and Xtensa 7 cores. I was busy traveling around the world doing the press introductions, so I got behind on my blogging. Here's some basic information. The web site is updated to reflect the new products.

Both processors feature several architectural enhancements, and are the first configurable licensable core families available with built-in, on-the-fly Error Correcting Code (ECC), which is extremely important in storage, networking, automotive and transaction processing applications where data integrity and error resiliency are of paramount concern. Tensilica’s new generation of processors reinforce Tensilica’s processor technology leadership by remaining the lowest power, highest performance licensable cores on the market. Both processors are available and shipping now.

See http://www.tensilica.com/news_events/pr_2006_12_04LX2.htm for highlights of what's new in these two processors.

Lauterbach’s TRACE32® PowerView Debugger Supports

Lauterbach now supports Tensilica’s Diamond Standard and Xtensa configurable processors with its TRACE32 PowerView microprocessor debugger. Lauterbach’s debugger speeds software development on Tensilica’s processor cores.

“Over the past year, we’ve seen increasing demand for our products on both families of Tensilica processors – the Diamond Standard series and the Xtensa configurable processors – as more designers are using these products in their SoC designs,” stated Norbert Weiss, International sales manager from Lauterbach. “Tensilica’s processors are particularly popular in multicore designs, which we service very well with our TRACE32-ICD.”

The PowerDebug (in-circuit debugger) is a high-performance JTAG debugger. The PowerDebug’s hardware consists of a universal debug module that can be connected to any PC or workstation via a USB 2.x or Ethernet interface. The PowerView software supports multicore debugging. Graphical variable displays and dedicated commands to handle large arrays support the development of DSP-specific code. The combination of the debugger and the PowerProbe logic analyzer enables real-time measurements. The PowerView debugger software provides a unified, graphical environment for debugging SoCs with one or more Tensilica processors, or a combination of Tensilica processors plus cores from other vendors in a heterogeneous debug environment.

Tensilica Offers Free Music Downloads to Showcase Quality of HiFi 2 Audio Engine

Tensilica, Inc. is offering free jazz music downloads in five popular music formats (MP3, WMA, MPEG-2/4 AAC LC, aacPlus™ v1, and aacPlus v2) from its web site at www.tensilica.com. Tensilica encoded the free music downloads utilizing the HiFi 2 Audio Engine encoders to showcase the fidelity achieved with a DSP processor core optimized for audio.

The two tunes available, “Les is Moore” and “Pigsaw Juzzle,” are from the Pigsaw Juzzle CD from the Hip Pocket Jazz Quintet (http://hippocket.jazzcombo.com). The Hip Pocket Jazz Quintet has been playing in the San Francisco Bay Area since 1989 and Pigsaw Juzzle marks the group's first all-original release. The cornerstone of Hip Pocket's philosophy is to create truly improvised jazz. All the musicians are in the same room at the same time and there are no overdubs.

See Diamond NetSeminar at Techonline

See Tensilica's newest NetSeminar at Technoline. "Using Diamond Standard Processors in AMBA-based SOCs" gives a great overview of our Diamond Standard processor family. It's free and can be viewed any time. Go to:
http://www.techonline.com/learning/livewebinar/400002

Tensilica Adds Ogg Vorbis Decoder to Popular Xtensa HiFi 2 Audio Engine

Tensilicahas added an Ogg Vorbis decoder for its popular Xtensa HiFi 2 Audio Engine and Diamond 330HiFi processor core. The Xtensa HiFi 2 Audio Engine is the most popular audio processor core on the market, designed into devices ranging from cellular phone handsets to prosumer audio. This year, Tensilica’s customers will ship tens of millions of products using the Xtensa HiFi Audio Engine. With this software decoder, the capability to play music encoded in the Ogg Vorbis format can be added to any chip that includes the Xtensa HiFi 2 Audio Engine. The Ogg Vorbis format is increasingly popular in video games and digital audio players because it is open source and royalty free.

For more information on the HiFi 2 audio engine, see http://www.tensilica.com/products/hifi_audio.htm
For more information on the Diamond Standard 330HiFi Audio processor, see http://www.tensilica.com/diamond/di_330hifi.htm

See Tensilica at GSPX

Tensilica will be delivering 3 presentations at GSPX, October 30-November 2, Santa Clara Convention Center:

Tuesday, 8 am - "MPSOC Flow for Multiformat Video Decoder based on Configurable and Extensible Processors" – Gulbin Ezer

Wednesday, 11 am - "Integrating IP in Multicore DSP/Processor SoCs "- panel on Multicore SOC design – Sumit Gupta

Thursday, 8 am - "Goodbye, Mr. DSP: DSP IP Cores are Superfluous for New SOC Designs" – Steve Leibson

NetEffect 10Gb iWARP Ethernet Channel Adapter Employs Multiple Xtensa Processors

Congratulations to NetEffect, Inc., for the recent introduction of its 10Gb iWARP Ethernet Channel Adapter (ECA). The NE010 is the first adapter on the market that fully implements the iWARP Ethernet standards, allowing data center managers to realize full 10 Gbps throughput using existing Ethernet hardware and software. NetEffect used multiple Tensilica Xtensa configurable processors in their impressive custom chip design for this adapter.

“We selected Tensilica’s Xtensa processors because of the ease with which we were able to optimize certain functions for our high-speed, demanding Ethernet channel adapters,” stated Rick Maule, NetEffect’s CEO. “Tensilica’s automated process let us optimize our embedded processors for our exact application in a fraction of the time that it would have taken us using other alternatives.”

For more info, see http://www.tensilica.com/news_events/pr_2006_10_24.htm

NuFront Software Picks Xtensa for DSP in China’s Mobile TV Handsets

NuFront Software of Beijing, China, is designing a complex system-on-chip (SOC) using Tensilica’s Xtensa configurable processor. NuFront is a leading design firm specializing in SOC designs for China’s digital television products. They are developing a baseband DSP (digital signal processor) for China’s Mobile TV handset standard, and are using the Xtensa processor because they can optimize it for the performance they need.

"Tensilica’s Xtensa processor was very attractive for our next design because standard processor cores couldn’t give us the performance we needed,” stated Hamilton Yong, COO, NuFront Software. “The only way to get the performance was to be able to optimize the processor, and Tensilica is the only company with the automated tools to make that customization much easier and ensure our success.”

EE Solutions Licenses Diamond Standard 108Mini Processor Core

EE Solutions (EES) of Hsinchu, Taiwan, a leading design service provider with considerable expertise in SOC (system-on-chip) design, has licensed the Diamond Standard 108Mini processor core for a high-performance, low-power application for one of its customers.

"Tensilica’s Diamond Standard 108Mini core perfectly met our needs for a low-cost, low-power, high-performance controller core for a high-volume customer application in the mobile space,” stated Jim Su, chief executive officer of EES. “We evaluated all of the popular 32-bit controller cores on the market, and Tensilica’s Diamond Standard 108Mini gave us the best price,performance and power solution.”

Afa Adopts Tensilica’s Xtensa Configurable Processor

Afa Technologies, Inc. (Afa) of Taipei, Taiwan, has selected the Xtensa configurable processor for a new multi-standard mobile digital TV receiver system-on-chip (SOC) design project. Afa is a fabless IC design house specializing in designs for DTV (digital television), cellular phones and digital home LANs (local area networks).

“We picked Tensilica’s Xtensa processor because we were very impressed with the ability to customize it, using the TIE (Tensilica Instruction Extension) language, for our demanding mobile TV demodulator application,” stated Philip Sun, Afa’s executive vice president. “Tensilica’s unique technology allows us to implement in low-power processors what previously was only possible using hardwired logic. By optimizing the Xtensa processor, we can deliver a programmable solution for advanced mobile TV handsets, and still meet the low power constraints needed to deliver the long battery life consumers expect.”

For more information, see http://www.tensilica.com/news_events/pr_2006_10_10.htm

Nethra Licenses Tensilica’s Diamond 108Mini Core Processor for Mobile Handset Imaging

Nethra Imaging, a privately held developer of imaging solutions for consumer applications, has licensed the Diamond Standard 108Mini processor core as the main system controller for its upcoming mobile handset imaging chip design.

“We picked Tensilica’s Diamond 108Mini over other processor cores because of the small code size, small area and ease of integration into our product development environment,” said Murty Bhavana, Nethra’s vice president of marketing. "Image and video capture and processing require very high performance imaging algorithms. Using a Diamond 108Mini to provide a high performance processor core, our customers will have enough headroom to add their IP and provide product differentiation."

For more information, see http://www.tensilica.com/news_events/pr_2006_10_03.htm

ThreadX RTOS for Tensilica’s Diamond Standard and Xtensa Processor Cores

Express Logic's popular ThreadX RTOS now supports all of Tensilica’s Diamond Standard and Xtensa configurable processor cores. The combination of ThreadX and Tensilica’s Xtensa is already production-proven in a high-volume SOC design used in personal laser printers.

ThreadX is a small-footprint RTOS with real-time determinism that enables Tensilica customers to support applications that demand high-performance, low overhead, and fast time-to-market. As a full port to all of the Tensilica products, ThreadX supports Tensilica’s on-chip coprocessors including its floating point unit, Vectra DSP engine and special Tensilica Instruction Extension (TIE) cases. The simplicity and low cost of ThreadX, including its royalty-free licensing, make it attractive for high-volume applications in consumer devices, office automation, medical equipment and networking. ThreadX has been widely embraced and is currently deployed in over 300 million electronic products.

For more info, see http://www.tensilica.com/partners/os_express_logic.htm

ProDesign to Provide ASIC Prototyping and Verification for Tensilica’s Diamond Standard Processors

Designers can now use ProDesign’s CHIPit ASIC Rapid Prototyping and Emulation systems to verify designs using Tensilica’s popular Diamond Standard processor cores. CHIPit verification platforms provide verification and validation through the SOC and ASIC project life cycle.

“We are working with Tensilica because a growing number of design teams are using Tensilica’s Diamond Standard processor cores,” stated Heiko Mauersberger, ProDesign’s chief technology officer. “The Diamond Standard cores deliver the best mix of low power and high performance for applications ranging from simple 32-bit controllers to high-end DSPs and an audio processor.”

ProDesign’s CHIPit ASIC Prototyping line provides an integrated set of tools with debug capabilities that provide a dual solution for hardware and software verification and validation throughout the product life cycle. The FPGA-based ProDesign CHIPit platforms can handle capacities up to 21-million ASIC gates and run at system speeds up to 200 MHz.

For more info, see http://www.tensilica.com/partners/hw_prodesign.htm

HARDI Electronics Provides ASIC Prototyping for Tensilica’s Diamond Standard Processors

ASIC designs using Tensilica’s popular Diamond Standard processor cores can now be prototyped and verified on the HARDI ASIC Prototyping System (HAPS). HARDI Electronics is now part of Tensilica’s Diamond Standard partners program.

“Our Diamond Standard processors have been prototyped and verified with great success on HAPS products by several of our customers and partners,” stated Larry Przywara, Tensilica’s director of strategic alliances. “Our customers appreciate the flexibility and cost-effectiveness that the highly modular HAPS products provide. HARDI is a solid platform for verifying multi-million gate ASIC designs.”

“HAPS is the ideal platform for customers of Tensilica’s popular Diamond Standard processors to use to prototype and verify their ASIC designs, as well as get a head start in generating embedded software,” stated Lars-Eric Lundgren, president of HARDI Electronics. “The HAPS system can scale from small projects to providing industry leading capacity for large ASIC designs, so it is suitable for any Diamond processor-based SOC prototype.”

Hear Chris Rowen on "On Design Radio"

Listen to Chris Rowen's interview (podcast) on "On Design Radio" at http://www.ondesignradio.com/podcast/

eInfochips Becomes Authorized Tensilica Processor Design Center

eInfochips has joined the Tensilica Xtensions Design Center Partner Program and is offering system-on-chip (SOC) design services for customers using Tensilica’s Xtensa configurable processors or Diamond Standard processor cores. eInfochips has design centers in the US and India and a proven track record in design services ranging from silicon design and verification to physical design as well as board design and embedded firmware development.

“We’re seeing an increased demand for Tensilica’s Xtensa and Diamond Standard processors in a wide variety of applications from current and potential new customers,” stated eInfochips VP of marketing Tapan Joshi. “Our expertise can help these customers get their new designs to market much faster. And we can provide the full range of services for Tensilica customers, from silicon design and verification to embedded firmware development and total system integration.”

See http://www.tensilica.com/news_events/pr_2006_09_19.htm for more information

iBiquity Digital Picks Tensilica’s Xtensa Configurable Processors for HD Radio

iBiquity Digital Corporation of Columbia, MD, has licensed Tensilica’s Xtensa LX configurable processors, including the market leading HiFi2 audio engine, to provide digital baseband and audio processing for many HD Radio™ receivers. iBiquity will also become a value-added reseller of Tensilica’s technology, bundling it into select iBiquity silicon Intellectual Property (IP) offerings marketed to major semiconductor companies.

iBiquity is the sole developer of digital HD Radio technology, providing the innovations that allow the transmission of digital audio and data along with existing AM and FM analog signals. Besides delivering vastly superior sound that virtually eliminates the static and hiss often associated with analog radio, iBiquity’s technology provides a platform for advanced new services including HD2 multicasting, enabling FM stations to broadcast multiple streams of unique programming over a single frequency. More than 3,000 stations in the U.S. are in the process of upgrading to iBiquity’s digital HD Radio technology, with nearly 1,000 on the air and approximately 350 offering HD2 multicast channels. In addition, the technology is gaining visibility throughout the world.

“We chose Tensilica’s configurable processor technology because it provided a common processor platform that could be optimized for both the digital baseband and audio portions of our design,” stated Gene Parrella, iBiquity’s vice president of IC Development. “We were also very impressed with Tensilica’s area and power efficient processor technology. Both silicon area efficiency and low-power for portability are essential for our customers.”

Great Video Article

See "Creating multi-standard, multi-resolution video engines using configurable processors" on CMP's Video/Imaging DesignLine:

http://www.videsignline.com/howto/videoprocessing/193000929

Fujitsu to Distribute Tensilica’s Diamond Standard Processor Cores

Fujitsu Microelectronics America, Inc. (FMA) has signed an agreement to distribute Tensilica’s Diamond Standard processor cores as part of Fujitsu’s ASIC intellectual property (IP) offering. All six of Tensilica’s Diamond Standard processors will be available to Fujitsu’s ASIC customers for seamless integration into new chip designs.

The processors range from a low-power 32-bit controller up to the industry’s highest performance digital signal processing (DSP) core and a multifunction audio processor that has been designed into millions of cellular phones. Under the agreement, Tensilica’s Diamond Standard processors will be available to Fujitsu’s ASIC customers via the company’s IPWare library and COT customer directly.

“Tensilica’s Diamond Standard processor family includes controllers for the entire range of design requirements, so our customers can select the version that is optimal for their ASIC and COT design,” said Jason So, senior director of COT and ASIC Business Group for Fujitsu Microelectronics America. “We are pleased to offer the processor family as part of our extensive portfolio of solutions.”

Chris Rowen talks at Memcon

Chris Rowen, president and CEO of Tensilica, will present “Configurable Processors: Driving Efficient and Flexible Memory and I/O in SOC Designs” at this week's Memcon conference at the Santa Clara convention center. His talk is on Wednesday, Sept. 13, at 2:30 pm. He will discuss how the use of configurable processors, often many processors, each part of the SOC design, can implement multiple functions, sharing common resources efficiently, and reducing both design time and silicon cost.

New Customer Gallery on Web Site

See our new customer gallery at http://www.tensilica.com/markets/customer_handsets.htm . Here you can see the latest products that include chips with Xtensa and Diamond Standard processors. You'll see cellular handsets, printers, scanners, entertainment devices, and products for network access, network infrastructure, storage networking and wireless USB.

Free Online Seminar

See the new online seminar we did with Mentor Graphics.

Mentor Graphics Seamless product has been named the premier co-verification tool for Tensilicas new Diamond Standard series of processor cores. Seamless provides designers with a virtual platform to debug hardware/software integration issues while increasing simulation throughput, thereby allowing designers to quickly validate that the system hardware and software are functionally correct before prototypes are manufactured.

This online seminar walks you through the basics of these two product lines, explaining how they work in conjunction with one another to provide a complete solution to SoC design complexity.

http://www.mentor.com/products/fv/events/multi_socs.cfm

Micrium uC/OS-II RTOS Support Now Available

Micrium’s uC/OS-II RTOS (real-time operating system) now supports Tensilica’s Diamond Standard and Xtensa configurable processors. A port of uC/OS-II is now available on the Micrium web site at www.micrium.com/tensilica. The popular uC/OS-II RTOS now can run on all of Tensilica’s Diamond Standard CPU and controller cores, including the Diamond Standard 108Mini, 212GP, 232L, and 570T, as well as most Xtensa configurations.

Patents

Tensilica products and technology are protected by multiple patents in the USA and other countries. For a complete list, see http://www.tensilica.com/company/patents.htm

Market Rapidly Embraces Tensilica’s Diamond Standard Processor Cores in 2Q06

As of the end of the second quarter of 2006, Tensilica licensed 12 Diamond Standard series cores. This number included 10 new customers who had not previously used Tensilica’s processor products. In most of these designs, the Diamond Standard processors are used as the main SOC (system-on-chip) controller or main DSP (digital signal processing) engine.

“For the customer who just wants a drop-in solution for fast deployment late in the design cycle, the Diamond Standard processors hit the market’s sweet spots,” stated Chris Rowen, Tensilica’s president and CEO. “The typical processor customer wants standard control or DSP functions in the smallest, most power-efficient form factor – and that’s what we have to offer. We’re particularly pleased that our Diamond Standard processor family opened up doors at new customer sites, expanding our reach in the SOC design community.”

More at: http://www.tensilica.com/news_events/pr_2006_07_18.htm

Tensilica Launches Campaign to Raise $20,000 for San Jose Ballet at DAC

Tensilica is launching a campaign to raise $20,000 for Ballet San Jose (California) at this year’s Design Automation Conference (DAC), July 24-27 at the Moscone Convention Center in San Francisco. By painting 10”x10” canvases, conference attendees will artistically contribute to giant murals, designed by German artist Lothar Krebs, that will be given to leading Silicon Valley companies that make substantial donations to Ballet San Jose. Ballerinas from Ballet San Jose will be assisting the artists in the Tensilica booth, number 3548, at the front of the North Hall.

"Every chip designer is, in many ways, an artist. So at DAC, we’re celebrating the artist within each of us by letting attendees paint parts of giant pictures that tell the story of chip design,” stated Chris Rowen, Tensilica’s president and CEO. “We’ll use this artwork to support another art – ballet. Ballet San Jose is an integral part of our Silicon Valley culture and deserves widespread support.”

During the 4-day DAC exhibition, attendees will be able to paint part of a different picture each day. To preview the pictures and find out more, see http://www.tensilica.com/company/DAC_2006.htm

Morgan Kaufmann Publishes Tensilica Book Targeting SOC Designers

“Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores,” by Steve Leibson, technology evangelist at Tensilica, is now available. The book is a no-nonsense guide to the design of 21st-century mega-gate SOCs using nanometer silicon and emphasizes a processor-centric system on chip (SOC) design style. “Designing SOCs with Configured Cores” also provides SOC designers with the most comprehensive assessment available of the practical aspects of configuring and using multiple processor cores to achieve their very difficult and ambitious price, performance, and power design goals.

The book, published by Morgan Kaufmann, provides SOC designers with a practical introduction to three basic techniques of modern SOC design: use of optimized standard CPU and DSP processors cores, application-specific configuration of processor cores, and system-level design of SOCs using configured cores as the key building block. The book has a list price of $59.95 and is available at www.books.elsevier.com.

PnpNetwork Licenses Diamond Standard 330HiFi and 212GP for Mobile Phone TV Chip Designs

PnpNetwork Technologies, Inc., of Seoul, Korea, has licensed two Diamond Standard processor cores for their digital mobile broadcasting chip designs for mobile consumer broadcast TV applications and video-enabled handset designs. PnpNetwork will use the Diamond Standard 330HiFi for high-quality audio processing and the Diamond Standard 212GP as a control processor for their chip designs. See press release for more details: http://www.tensilica.com/news_events/pr_2006_07_06.htm

NVIDIA GoForce 5500 Employs Tensilica’s Xtensa HiFi 2 Audio Engine

The Xtensa HiFi 2 Audio Engine drives the high-quality 24-bit audio processing in the recently introduced NVIDIA GoForce 5500 handheld graphics processing unit (GPU). The NVIDIA GoForce 5500 brings high-fidelity surround sound as well fluid digital TV, rapid multi-shot photography and console-class 3D graphics to mobile phones. Phones based on the NVIDIA GoForce 5500 handheld GPU are expected to be available from key handset manufacturers before the 2006 holiday season.

For more information, see: http://www.tensilica.com/news_events/pr_2006_06_27.htm

Chris Rowen's Keynote at 2006 World Congress

Over 500 people attended Chris Rowen's keynote address to the 2006 World Congress in Computer Science, Computer Engineering, and Applied Computing in Las Vegas last Monday, June 26. His presentation is titled, "The Reinvention of the Microprocessor". If you missed it, you can see a PDF of the presentation at:
http://www.tensilica.com/pdf/Reinvention%20CD.pdf

Silistix Partners with Tensilica to Develop a Demonstration Test Chip for Portable Multimedia Applications

Silistix and Tensilica are collaborating on a demonstration chip for low-power, portable multimedia applications. The CMOS chip will demonstrate the ability of the Silistix CHAIN self-timed interconnect technology to work with high-performance processor cores from Tensilica along with additional silicon cores from Denali and sci-worx at a 65nm process node. For more information, see http://www.tensilica.com/news_events/pr_2006_06_26.htm

WiQuest Licenses Xtensa for Low-Power Wireless USB Chip Design

WiQuest Communications, Inc. has deployed the Xtensa configurable processor in WiQuest’s WQST110 ultrawideband (UWB) wireless USB chip design. “We licensed the Xtensa processor because it was the lowest power processor on the market, which is essential for wireless designs,” stated Greg Christison, vice president of Engineering, WiQuest Communications. “We were also impressed with Tensilica’s automated capabilities for configuring the processor."
Read more about what Greg Christison had to say at:
http://www.tensilica.com/news_events/pr_2006_06_22.htm

Neterion Renews Tensilica Xtensa LX Configurable Processor License

Neterion renewed its license for Tensilica’s Xtensa LX configurable processor. Neterion is the market leader in the 10-gigabit Ethernet adapter market, and is using the Xtensa LX processor for next-generation designs.

"Tensilica’s automated configurable processor design approach gives us the speed we need with lower power and smaller die size,” stated Dennis Shwed, Neterion’s vice president of hardware engineering. “Tensilica’s Xtensa LX processor delivers the performance levels required for demanding 10-gigabit Ethernet in high-speed server and storage networking applications.”

For more information, see http://www.tensilica.com/news_events/pr_2006_05_31.htm

New Books Showcase EDA and IC Design Methodologies

The new “Electronic Design Automation Circuits Handbook,” edited by Grant Martin, Tensilica’s chief scientist, Louis Scheffer of Cadence Design Systems and Luciano Lavagno of Cadence Berkeley Laboratories, is a 2-book reference that provides a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits. Several of the chapters in this authoritative work were contributed by experts at Tensilica. Find out more about these exciting books at http://www.tensilica.com/news_events/pr_2006_05_30.htm

Tensilica granted 8 new patents

Tensilica has been granted eight new configurable processor technology patents. Tensilica now holds a total of 10 patents on configurable processor technology as well as several fundamental patents on processor architecture, Tensilica also has several other patents pending.

“In all, Tensilica’s 10 patents make nearly 450 claims of inventions in the rapidly evolving field of configurable-processor technology,” stated Tom Halfhill, senior analyst for In-Stat’s Microprocessor Report. “Although judging the strength of a patent portfolio by counting claims is like measuring microprocessor performance by counting megahertz, the large number of claims does indicate that Tensilica is staking out a great deal of territory.”

For more information, see http://www.tensilica.com/news_events/pr_2006_05_22new.htm

Key Tensilica Configurable Processor Patent Strengthened

Tensilica's US patent number 6,477,683, “Automated processor generation system for designing a configurable processor and method for the same,” issued in November 2002 and anonymously challenged in May 2003, has not only withstood the challenge without modification, but 102 additional claims were also accepted into the patent by the United States Patent and Trademark Office (USPTO). This broad patent has been confirmed against the best-known prior art, creating an unusually strong foundation for Tensilica’s Xtensa configurable processor product line.
“The challenge has largely backfired,” stated Tom Halfhill, senior analyst for In-Stat’s Microprocessor Report. “The anonymous challenge has almost certainly strengthened this key patent. Having survived a lengthy reexamination and emerging with almost twice as many claims, it is unlikely to be challenged again.”

Aquantia Licenses Diamond Standard 108Mini for Next-Generation 10GE Over Copper IC

Aquantia Corp. of Milpitas, Calif., has licensed the Diamond Standard 108Mini processor core for their 10 Gigabit Ethernet physical layer transceiver chip design. Aquantia is developing chips which will enable the upcoming 10GBASE-T standard for operation over familiar UTP (Unshielded Twisted Pair) cabling.

"We liked Tensilica’s Diamond 108Mini because it gave us the performance we needed in a small form factor,” stated Ramin Shirani, vice president of engineering, Aquantia. “With its small footprint and minimal power requirements, the Diamond 108Mini is well suited for general control applications."

For more information, see http://www.tensilica.com/news_events/pr_2006_04_19.htm

Lucid Licenses Diamond 212GP Controller Core

Lucid Information Technology, Ltd., of Kfar Netter, Israel, has licensed Tensilica's Diamond Standard 212GP general-purpose processor core for a new scalable multi-GPU chip design project. The Diamond 212GP is a flexible mid-range RISC controller that includes instruction and data caches, a 16-bit multiply-accumulator, DSP functions and zero-overhead loop support. The Diamond 212GP also includes a single-cycle latency local interface bus. This processor core provides 40 percent better performance and 30 percent lower power than an ARM946E-S processor.

"We particularly liked the in-bound DMA capability of the Diamond Standard series,” stated Moshe Steiner, CEO, Lucid. “With this feature we are able to realize significantly higher computational and data throughput when compared to alternative architectures."

For more information, see http://www.tensilica.com/news_events/pr_2006_04_18.htm

See Diamond SW Tools Demo

Want a peek at the great software tools for our Diamond Standard series? Then check out Demos on Demand at www.demosondemand.com/dod/proddemos/vendors/pd_tensilica.aspx

Free Diamond Core Software Development and Modeling Tools

Tensilica is offering free evaluation versions of the Diamond Standard Software Toolkit, the advanced software development and modeling environment for the Diamond Standard processor core family, which was announced on February 20, 2006. The Toolkit is available for immediate download from Tensilica’s web site at www.tensilica.com.

Software and firmware engineers will want to explore the Diamond processor software development tools to learn how easy it is to port application code to the Diamond core processor family, and to experience the code performance and code size advantages of the Tensilica Xtensa instruction set architecture. Powerful visualization tools enable software developers to graphically view and compare profiling results.

Hardware design teams will want to take advantage of this free evaluation to experiment with the clock-cycle accurate, pipeline-modeling instruction set simulator and the associated performance modeling visualization views within the graphical user interface that show pipeline activity, cache utilization rates, and cycles spent on bus cycle activity.

Tensilica and CSIP of Ministry of Information Industry (MII) of PRC Establish First Joint IP Core Lab

February 23, 2006 - Tensilica, Inc. and CSIP of Ministry of Information Industry (MII) of PRC today announced the establishment of a joint IP core lab during a signing ceremony attended by Ding Wenwu, director of the Product Department of MII, Dr. Qui Shangin, head of CSIP, and Chris Rowen, president and CEO of Tensilica.

“It is our great honor to be the first company to set up an IP core lab with CSIP,” stated Chris Rowen, Tensilica president and CEO. “We will strive to provide world leading processor technology for Chinese clients through this lab so as to accelerate China’s SOC design and create more ICs with independent IP.”

For more information, visit http://www.tensilica.com/news_events/pr_2006_02_23.htm

Tensilica Introduces Diamond Standard processors

Tensilica introduced the Diamond Standard family of processor cores, a set of six off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to high-performance DSPs, all of which lead the industry in their respective categories both in lowest power and highest performance. The Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners. They are available directly from Tensilica and through a growing list of ASIC and foundry partners.

This announcement provides Tensilica with the broadest range of off-the-shelf processors in the industry, with the six Diamond Standard cores plus an almost infinite number of processor configuration possibilities for those customers requiring optimized, application-specific processors with Tensilica’s award-winning Xtensa configurable processor family.

For a full list of all Diamond press releases, see http://www.tensilica.com/news_events/press_releases_2006.htm.

Tensilica Establishes India Subsidiary for R&D

Tensilica has set up an Indian subsidiary to conduct fundamental, innovative research and development work for its industry leading configurable processor technology and to be closer to key customers in India. Engineers are already working on critical technology for Tensilica’s Xtensa configurable processor product line at this R&D center, Tensilica Technologies India, located in Pune. For more information, read: http://www.tensilica.com/news_events/pr_2006_02_09.htm

u-Nav Microelectronics Picks Xtensa for GPS Designs

u-Nav Microelectronics, a worldwide leader in ultra-low power Global Positioning Systems (GPS) semiconductors, has picked the Xtensa configurable processors for its next-generation GPS designs, which will be targeted for portable applications such as mobile wireless handsets and consumer devices.

“We selected the Tensilica Xtensa processor because they offered us the most flexibility and achieved the lowest power for a programmable solution,” stated Greg Winner, COO of u-Nav Microelectronics. “With the ability to customize Xtensa through Tensilica’s automated processor generation technology, and the inclusion of u-Nav’s custom instructions, we created a unique way to significantly lower the total power consumption of our complete GPS system-on-chip design.”

For more, see http://www.tensilica.com/news_events/pr_2006_02_06.htm.

MediaWorks and Olympus renew licenses

Both MediaWorks and Olympus renewed their licenses for Tensilica's Xtensa processors.

MediaWorks employs Xtensa processors in their recently announced groundbreaking MediaFlex™ platform architecture and MW301 Media Processor. See http://www.tensilica.com/news_events/pr_2006_01_25.htm
for more information.

Olympus is making its Tensilica license, which now has been expanded to include Xtensa LX, available to its design groups in its Corporate R&D Center in both Japan and the United States. See
http://www.tensilica.com/news_events/pr_2006_01_16.htm
for more information.