FS2 Debugger Now Available

The FS2 System Navigator is available now for debug and system integration of system-on-chip (SOC) designs with Tensilica Xtensa V and Xtensa LX configurable and extensible processors. The FS2 System Navigator tool supports designs that employ multiple Xtensa processors – a hallmark of the Tensilica architecture. The FS2 System Navigator architecture offers optional interfaces for FS2 Bus Navigator tools, which provide tracing and bus level analysis of OCP, AMBA, or custom bus interfaces. For more information, see http://www.tensilica.com/html/pr_2005_03_29.html .

Tensilica Tops EEMBC OA Benchmark

The Xtensa LX configurable processor posted the highest score ever recorded for a licensable processor core, and the highest absolute score ever published for any processor, on the Office Automation benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC). The EEMBC benchmark scores, independently certified by the EEMBC Certification Laboratories (ECL), confirm that the Xtensa LX processor is nearly four times faster than the much larger PowerPC 440GX core, and more than 4 times as powerful as the 64-bit MIPS 20Kc processor.

The certified EEMBC OAmark scores are:
· 4.19523 – Optimized Xtensa LX processor
· 1.07999 – Out-of-the-box PowerPC 440GX processor
· 0.98880 – Out-of-the-box Xtensa LX processor
· 0.89033 – Out-of-the-box MIPS 20Kc processor
. 0.75975 – Out of the box ARM 1026EJ-S processor

For more detail, see http://www.tensilica.com/html/pr_2005_03_28.html .

Book by Chris Rowen

“Engineering the Complex SOC,” by Chris Rowen, CEO of Tensilica, and editor Steve Leibson, Tensilica’s Technology Evangelist, describes an emerging SOC design methodology that uses configurable, extensible processors as basic building blocks. This allows chip designers to finish larger projects in much less time, with higher quality results. The book uses real-world illustrations extensively, both in the form of case studies about architecture decisions and in short examples that communicate the flavor and the power of these methods. Find out more about this powerful book at http://www.tensilica.com/html/book.html .

MPR Names Xtensa LX the “Best IP-Core Processor” of 2004

The Xtensa LX processor has won the 2004 Microprocessor Report (MPR) Analysts’ Choice Award for Best Intellectual-Property (IP) Core. MPR selected the Xtensa LX core for its market-leading performance (verified by independent benchmark results), low power consumption, unmatched architectural flexibility, powerful Vectra LX DSP engine and unique XPRES (Xtensa PRocessor Extension Synthesis) design tools.

“We saw significant activity in the IP-core market this year with many companies announcing new products, but Tensilica’s introduction of the Xtensa LX and its revolutionary tool, the XPRES design compiler, made it the clear winner,” said Tom R. Halfhill, Senior Analyst, Microprocessor Report. “Even without XPRES, Xtensa LX would be the leading contender for this award, but the combination is unbeatable.”

Read the article from MPR at http://www.tensilica.com/Best_Processor_Core_2004.pdf

Great Synopsys Users Group (SNUG) Event

Last night, Tensilica had a booth at the annual Synopsys Users Group vendor fair at the Santa Clara Marriott. As usual, Synopsys had lots of great food and drinks. The ballroom was full of booths from various companies that fit into and around the Synopsys design flow. We heard that this was the most attended SNUG yet, with over 1,000 registered attendees. The room certainly was packed, and lots of people stopped by to see us. We had a demonstration of our XPRES tool, which takes a standard C/C++ algorithm and automatically configures an Xtensa LX processor to run that algorithm at RTL-equivalent speeds.

NEC Electronics America Distributes Xtensa

“The Xtensa processors are a welcome addition to NEC Electronics America’s ASIC IP library. Their customization capabilities make them ideal replacements for blocks of logic that previously would be handcrafted in Verilog or VHDL. By using processors instead of logic blocks, our customers will benefit from the inherent programmability, reduced verification time and much faster design times,” said Phillip LoPresti, associate vice president and general manager, custom LSI strategic business unit, NEC Electronics America. For more information, see http://www.tensilica.com/html/pr_2005_03_14.html

New White Papers on FLIX and XPRES

Find out more about two of Tensilica’s most exciting technologies:

http://www.tensilica.com/FLIX_White_Paper_v2.pdf - FLIX: Fast Relief for Performance Hungry Embedded Applications

http://www.tensilica.com/XPRES-Triple-Threat_Solution.pdf - XPRES Compiler: Triple-Threat Solution to Code Performance Challenges

Tensilica Expands into China

“We are pleased to establish a direct presence in China where we can work closely with the systems and semiconductor companies to help them differentiate and innovate using our automated design approach,” said Chris Rowen, president and CEO of Tensilica. More information: http://www.tensilica.com/html/pr_2005_03_10.html

FS2 Offers Multi-Core Debugging

The FS2 System Navigator tool supports designs that employ multiple Xtensa processors – a hallmark of the Tensilica architecture. The FS2 System Navigator architecture offers optional interfaces for FS2 Bus Navigator tools, which provide tracing and bus level analysis of OCP, AMBA, or custom bus interfaces. See http://www.tensilica.com/html/pr_2005_03_08.html

New VP of Customer Engineering

Dan Weed is New VP, Customer Engineering

Dan will be responsible for organizing and managing Tensilica’s technical support and customer engineering operations. He has more than 25 years experience in design center management, marketing and engineering at Cadence Design Systems, LSI Logic, Fujitsu Microelectronics and Texas Instruments. See http://www.tensilica.com/html/pr_2005_03_07a.html