Tensilica White Paper: TIE - The Fast Path to High Performance Embedded SOC Processing

There's a powerful way to optimize an Xtensa processor-through a processor-description language called TIE, Tensilica's Instruction Extension language. TIE is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.

This short White Paper introduces the core ideas behind TIE. You'll see that TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor's performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power.

Tensilica's CEO Jack Guedj on Hogan's Heroes DAC Panel Next Tuesday

Jim Hogan brings together an A-list of industry luminaries to discuss "Learning from Apple" at 10 am next Tuesday in booth 310. We assume his panel will be standing room only as it always is one of the big highlights of DAC. See you there!

Why is there a For Lease sign in front of Tensilica's HQ?

Because we're growing like crazy and we've finally outgrown our building! We're moving to a much bigger 2-story building across the street mid-July.

Tensilica Discusses Importance of Customizable IP Subsystems at Semico IMPACT Conference

This Wednesday from 3-4:15 pm, Steve Roddy will participate in a panel discussion titled, "Will IP Subsystems Help Reduce Complexity... At What Cost?" at Semico's IMPACT Conference: Focus on The IP Ecosystem. The panel will look at the evolution of complex SoC architectures and the role of IP subsystems in this growth.
Need a ticket? Let me know. Details on the conference are here.

Tensilica and VWorks Partner to Provide Virtual Prototyping Platforms

As part of the collaboration, Tensilica's DPU models are integrated with the VLAB virtual platform simulation environment from VWorks, providing early access, high performance and direct software debug capability. Software and services are provided by VWorks and its service partner ASTC.
See press release.

Tensilica and Sensory Working on Hands-free Voice

Tensilcia and Sensory are working on HW/SW technology that will allow you to say commands to your smartphone - even if it is turned off. Imagine what this could do for disabled people. Read the article.

See Tensilica at the ChipEx Conference in Israel May 1-2

Stop by the Tensilica booth if you're going to the ChipEx Conference in Israel. This is Tensilica's first time exhibiting at this conference, and we're very excited. Israel is a key market for us and we just hired our first field application engineer in Israel, who will be working in our booth. Stop by and say hello.

Tensilica Expands Dataplane Processor R&D Center in Pune, India

Tensilica plans to increase headcount by at least 50 percent in the next year. Over the past six years, employees at Tensilica's Pune R&D center have become essential developers of Tensilica's dataplane processors (DPUs), which are used by chip designers to perform complex signal processing tasks, such as audio and baseband processing.

"The engineers in our Pune design center are an integral part of our R&D team, and they've tackled some of the most demanding projects," stated Jack Guedj, Tensilica's president and CEO. "We've asked them to take on several challenges and they've proven they have the background to do an excellent job in many engineering areas."
See press release

Tensilica Adds Support for Dynamic Resolution Adaptation Audio Standard to HiFi Audio DSP Library

We've added support for the Dynamic Resolution Adaptation (DRA) standard. Now all products that include the HiFi Audio DSPs can be used to support the standard approved by the People's Republic of China as the National Audio Standard (GB/T 22726-2008) for multi-channel audio decoding. Tensilica has delivered the HiFi DRA decoder to a number of Tier 1 system OEMs and semiconductor companies.
See press release.

Tensilica Reaches Audio DSP Milestones: 300 Million HiFi Audio/Voice DSPs, Over 100 Software Packages, More Than 30 Partners

"The 300-million milestone is just the tip of the iceberg," stated Larry Przywara, Tensilica's senior director of multimedia marketing. "By 2014 we expect to ship approximately one billion HiFi cores a year. The need to support a wide range of software packages, and the large costs associated with the support and maintenance, has resulted in many companies deciding to use our standard audio/voice DSPs. Plus, we've automated the process of customizing all of our IP cores so companies can add essential features to differentiate their cores if required."
See press release.