Wolfson Licenses Tensilica's Hifi EP Audio

Goal: create a low-power, high definition sound platform. Combining Wolfson’s world-leading mixed-signal technology and audio expertise with Tensilica’s innovative HiFi audio digital signal processor (DSP) cores, this licence agreement will bring HD sound to multimedia platforms, including mobile handsets, netbooks, smartbooks, digital TVs and other multimedia devices.

With HD video a well-established standard in today’s consumer electronics world, this partnership will set the benchmark for HD sound and address consumer demand for crystal clear audio.

Resolving the Grand Paradox: Low Energy and Full Programmability in 4G Mobile Baseband SOCs

Click on the headline above to see Dr. Chris Rowen's presentation at the CoolChips conference in Yokohama, Japan (the presentation is in English) on April 15.

ConnX 545CK DSP Core Gets Faster, Smaller, Lower Power

Our third-generation ConnX 545CK 8-MAC VLIW DSP core for SOC designs delivers up to 20% faster clock speed, 11% smaller die area and up to 30% lower power consumption.

See our Product page as well and download the product brief.

Xtensa 8 or Xtensa LX3 - Which is Right for You?

Xtensa LX3 is a super-set of all Xtensa 8 features. But do you really need them all? Check out this page to see which one is best for your application.

Ultra-Low-Power Software-Defined Radio for LTE Wireless Baseband

See Dr. Chris Rowen's presentation to the IEEE Silicon Valley chapter meeting, where he discussed the embedded systems challenges to SDR.

Two Application Engineering Jobs Open - Plus More

We have an applications engineer job open in Santa Clara, CA, USA, and an audio specialist at our office in Pune, India. See our full list of job openings.

Free ThreadX Eval Download

Express Logic's popular ThreadX RTOS supports all of Tensilica's Diamond Standard and Xtensa configurable processor cores. The combination of ThreadX and Tensilica’s Xtensa is already production-proven in a high-volume SOC design used in personal laser printers.

ThreadX is a small-footprint RTOS with real-time determinism that enables Tensilica customers to support applications that demand high-performance, low overhead, and fast time-to-market. As a full port to all of the Tensilica products, ThreadX supports Tensilica’s onchip coprocessors including its floating point unit, Vectra DSP engine and special Tensilica Instruction Extension (TIE) cases. The simplicity and low cost of ThreadX, including its royalty-free licensing, make it attractive for high-volume applications in consumer devices, office automation, medical equipment and networking. ThreadX has been widely embraced and is currently deployed in over 300 million electronic products.

White Paper: A Designer’s Guide to HD Video Pre- and Post-Processing

HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.

Updated White Paper: Everything You Wanted to Know about SOC Memory

This paper discussed the many alternatives for on-chip and off-chip memory usage that SOC designer must understand. It discusses the essentials of memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory.

Using Multiple Processors in the SOC Dataplane

There are several advantages to using multiple processors as SOC task building blocks. One of the biggest is that processors are inherently programmable, so functional changes can be made to the chip’s operation using firmware after the chip design is finished and even after the chip has been fabricated. Complex state machines can be implemented in firmware running on the processors, greatly reducing verification time.

In addition, a multiple-processor-based design approach promotes the flexible sharing and reuse of on-chip memories while reducing the overall amount of memory needed.

Design with multiple processors facilitates system modeling with instruction-set simulators, which are much faster and more efficient than RTL-based system simulation. Read more about it here.