White Paper: How to Increase ASICs and SOC Computational Performance with Long-Word Processors

VLIW processors execute multiple independent instructions each clock cycle and provide a tremendous performance boost per clock cycle without incurring the exponential power-consumption increase caused by clock-rate increases. However, VLIW architectures have their own problems, particularly code bloat, which causes code footprints to balloon-thus increasing memory costs.

The Xtensa LX processor uses an innovative approach to VLIW design called FLIX (Flexible Length Instruction eXtensions), which gives ASIC and SOC designers more options for cost/performance tradeoffs. FLIX technology provides the flexibility to develop ASIPs (application-specific instruction-set processors) that freely and modelessly intermix smaller RISC instructions with multi-operation FLIX instructions. Read our white paper.

IntegrIT's DSP Math Library Ported to Tensilica's Baseband DSPs

The IntegrIT NatureDSP Math library simplifies the software development process for design teams that want to port their own signal processing application software to the ConnX BBE16 DSP.  The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for implementation of typical digital signal processing functions including highly optimized routines for filtering, FFT, matrix, trigonometric and other math operations.
Read the press release.

White Paper: Optimizing a DSP Architecture for Wireless Baseband

The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations. Read the white paper.

Tensilica Participates in Synopsys TLMCentral Web Portal for Transaction-Level Model Access

TLMCentral aggregates information about free and commercial system-level models of common system-on-chip (SoC) components from leading semiconductor IP vendors, tool providers, service companies and universities. TLMCentral is an open portal that will ease and accelerate the development of virtual prototypes across the industry. It is available at no cost to users and providers of transaction-level models.

Transaction-level models raise designer productivity by increasing the level of abstraction at which they design. TLMs are predominantly used in virtual prototypes which allow engineers to accelerate their software design schedules by up to nine months and significantly improve the productivity of their software development, hardware/software integration, and system validation tasks. Transaction-level modeling has also contributed to significant productivity gains in architecture design and SoC verification, and the models aggregated on TLMCentral can be applied to those use cases as well. See Synopsys news.

Software Defined Everything - Tensilica's Grant Martin's latest blog

Tensilica's Chief Scientist Grant Martin discusses the challenges of getting the right mix of hardware and software for hardware defined radios. Read his blog post.

Fraunhofer ISS is Tensilica's Newest Authorized Design Center Partners

Wow. If you need someone with tons of experience in audio and multimedia technologies, look at Fraunhofer.

“We look forward to working closely with Tensilica and the wide customer base using Tensilica’s HiFi Audio DSPs, especially for home entertainment, automotive and mobile multimedia,” stated Marc Gayer, head of Embedded Audio at Fraunhofer IIS. “Tensilica’s HiFi Audio DSP architecture is extremely efficient with industry best area and power requirements.” See press release.

Tensilica Now Hiring in Israel

We're looking for a great Field Applications Engineer. Learn more about this posting here.

Visit Tensilica's Linux Wiki Pages

Yes, several Tensilica customers run Linux on their Tensilica IP cores. And we collect information on how best to do that at our Wiki. We've seen Linux running on cores with up to a gigabyte of memory. And while most of our processors run without operating systems in the dataplane, why not match up those dataplane cores with a Tensilica main control processor running Linux as well. Then all the cores will be using the same software tool chain.

Tensilica Customer TranSwitch Announces LTE™ Fixed Wireless Residential Gateway Solution

Last week TranSwitch announced the availability of a new LTE (*Long Term Evolution; a 4G wireless broadband technology) fixed wireless reference design that enables wireless providers to deliver broadband voice, video and data services to homes and enterprises. TranSwitch’s reference design incorporates its Atlanta 2000™ processor and complete software solution which is designed for high performance, real time services under real world network conditions.  The Atlanta 2000 includes Integrated dual RISC cores: 400 MHz Tensilica Xtensa LX with MMU.

Three More Jobs Posted at Tensilica

Check out our full list (we're up to 17 jobs posted now) and see if you know someone that can help Tensilica grow. We're looking for people in Beijing, Pune and Santa Clara.