Tensilica Excels in Heavy Duty Networking Equipment

Line rates are on the rise, protocol standards are evolving, and you're being asked to add high-value Internet services such as VoIP, IPTV and video on demand. For intense communications and storage applications, you need fast, flexible processing engines that can be adapted to the exact datapath that needs to be efficiently processed. That's why companies like Cisco, Astute Networks, Bay Microsystems, Broadcom, Juniper Networks, NEC, NetEffect and Plato Networks picked Tensilica's DSPs and cores.

Look at All the Places Where You Can Find Tensilica's IP Cores in the Handset

Audio, baseband PHY and MAC, other radio interfaces, imaging, fingerprint and biometric processing, security, decryption, embedded control - these are some of the functions where you'll find Tensilica's IP cores employed in the handset.

Updated White Paper: How to Minimize Energy Consumption while Maximizing ASIC and SOC Performance

Power has become a first-order concern for ASIC and SOC designers right next to performance and area, whether the design is for portable mobile devices, for networking boxes, or for any other application. Optimizing a design for energy at an application and system level has the potential to cut processor and local-memory energy requirements by as much as half in many cases through intelligent design trade-offs. The amount of power savings made at the early architectural level far outweighs any potential power savings that might be made later at the RTL or physical design levels.

Tensilica Offers More DSP Choices than Any Other IP Company

Everybody's DSP requirements are different. Instead of trying to figure out how to squeeze your requirements into a DSP core that doesn’t quite match your needs, Tensilica gives you lots of choices - as a matter of fact, Tensilica offers an almost unlimited range of DSPs. How can we do this? You can pick from several pre-defined function blocks in our ConnX DSP family or you can design your own to exactly match your application.

The Challenge of Moving Data Into and Out of the Processor

Interesting article in the New York Times titled "Remapping Computer Circuitry to Avert Impending Bottlenecks." It suggests new ideas on alternatives to the bottleneck created by the need to move data into and out of the system bus. Great, interesting ideas, but what about changing the fundamental load/store architecture we've all grown to know and love? Tensilica has three major ways to let you bypass the bus altogether and stream data through the processor. Check them out.

Updated White Paper: Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design

Processor buses are increasingly inadequate for high-throughput applications such as video compression/decompression or high-speed networking. A new, configurable feature called "ports and queues," , based on tried-and-true system technology, provides the ASIC and SOC design team with as much bandwidth as any system can possibly use, essentially unlimited I/O bandwidth.

New Job Posting: Senior Baseband DSP SW Engineer, Santa Clara, CA USA

We are looking for a versatile Senior Baseband DSP Software Engineer.  As part of Tensilica's baseband DSP team, you will be responsible for specifying, designing, developing, testing and releasing libraries for baseband communications targeted to a heterogeneous family of baseband DSPs.  The work is carried out both by Tensilica engineers and a network of strategic third party software development partners.  As a result, much of the work will involve detailed technical interaction with these third party software partners, in order to ensure the rapid availability of basic DSP libraries and ported baseband stacks at PHY, MAC and other layers of communication SW targeted to our DSPs.  The work will range from very detailed technical development to external partner relationship development, and you will have a strong influence on the future development of new baseband DSPs at Tensilica.

New white paper: Optimize SOC Performance Using Memory Tuning and System Simulation

Memory tuning lets you choose memory-related parameters for each on-chip processor core to balance system performance, processor area, and memory size by exploring a target application's sensitivity to these memory system issues.

New Job Posting: Sr. Design Verification Engineer - Santa Clara, CA USA

See our entire list of engineering jobs open at our headquarters in Santa Clara and our R&D facility in Pune, India. We're looking for top talent!

EE Journal Reviews Audio IP Cores

The ever increasing complexity of audio software (Tensilica now supports over 80 encoders, decoders and audio-enhancement packages) means that most companies are picking audio-specific IP cores rather than trying to design the cores themselves. Bryon Moyer's overview of audio IP cores does an excellent job of overviewing the complexity involved in audio applications. Read this article, then check out Tensilica's HiFi Audio.