ConnX D2 DSP Engine Combines Outstanding Performance, Compact Size, and Easy Programmability

New today - the high-performance, small, low-power ConnX D2 16-bit dual-MAC DSP engine for SOC designs. The ConnX D2 DSP engine provides uncompromised performance from C code, unlike many other DSPs that require time consuming assembly coding for maximum performance. This means that virtually any C program, including those written with C intrinsic functions for the TI C6x family or ITU (International Telecommunications Union) reference code, can run unmodified and with excellent performance on the ConnX D2 DSP engine. Find out more at http://www.tensilica.com/news/296/330/Tensilica-s-ConnX-D2-DSP-Engine-Combines-Outstanding-Performance-Compact-Size-and-Easy-Programmability.htm

Apnote: Multiple Audio Codec Operation

This application note describes a multi-stream audio decoder test bench that works without needing a threading operating system. A software test bench is provided for the Diamond 330HiFi processor that supports decoding and audio mixing of an arbitrary number of homogenous or heterogeneous audio streams. This application note describes the test bench, and discusses the coding techniques used to reduce memory requirements and to synchronize/mix audio decoded from multiple streams.
http://www.tensilica.com/products/literature-docs/application-notes/audio-application-notes/multiple-audio-codec.htm

New Ap Note on TIE Ports

Why do so many designers pick Tensilica's Xtensa LX? TIE Ports are an important part of the answer. They let you bypass the bus and connect directly, much like GPIO. Read this application note and find out how you can significantly increase I/O speed, unlike any other processor core.

Microprocessor Report Reviews ConnX Baseband Engine

See the 9-page in-depth review of Tensilica's new ConnX Baseband Engine written by Tom Halfill of Microprocessor Report (http://www.mdronline.com/mpr/index.html). If you are not a subscriber, email paula@tensilica.com for your free pdf of this important review.

White Paper on Digital Audio

Whitepaper: Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

Digital audio has rocketed to the top of the critical features list for all sorts of products over the past several years. At the same time, the number of digital audio codecs and audio-enhancement programs has exploded. Now most consumer products must support multiple codecs and offer a broad range of audio-enhancement features.

This has created high demand for a flexible, high-performance, low-power audio engine that adds sound to an SOC's design with the least amount of design effort and a small on-chip footprint. Tensilica's HiFi 2 Audio Engine was carefully crafted to meet the requirements for the broadest possible range of consumer products, from mobile music players to in-home high-end entertainment centers. Read the white paper:
http://tinyurl.com/nop5bl

Ap note: Implementing the Advanced Encryption Standard on Xtensa Processors

This application note examines the Advanced Encryption Standard (AES) cipher and illustrates the power of a configurable processor in accelerating encryption and decryption. Xtensa-based application-specific processors are quickly designed, simulated, and instantiated in silicon. These processors offer performance that rivals hardware solutions along with the benefits of flexibility, programmability, and ease of verification found with purely software implementations. The processor extensions proposed in this application note give the Xtensa processor a speedup of over 300x compared to a base Xtensa processor or a similar 32-bit RISC engine such as ARM9, MIPS32, etc. See http://www.tensilica.com/products/literature-docs/application-notes/tie-application-notes/advanced-encryption-standard.htm

Tensilica Great Race Results

Tensilica great race results: First place: Brian Withers. Second place: Jack Guedj. Third place: Stuart Fiske - the prize? A bottle of Champaigne - the drink of champions

Tensilica's "Great Race" today

This afternoon at 3 employees will meet for Tensilica's "Great Race". Walkers and runners will be entered into a raffle for a grand prize. Wonder what it is?

Design Automation Conference (DAC) wrap-up

I went up to San Francisco yesterday (Tuesday) to attend DAC. I heard it was much busier on "free" Monday. It was pretty quiet yesterday, but that's because a lot of the good activity is happening in vendor suites or in the technical sessions. That leaves little time to wander the halls. Many booths were just front-ends to the suites, where the action was happening as vendors gave demos of new tools and capabilities. People with little companies with small booths and no suites looked like they were getting pretty bored with the lack of hall traffic. There were very few flashy booths - the XJTAG girls in their short skirts were about as exciting as it got. Why don't they just let qualified people in for free every day? The more traffic, the better the show.

Synopsys and Cadence issued press releases about their efforts to create workable tools for 32 nm designs - let's hope they can really make their tools work. The show is still going on today at Moscone center.

Virtutech Now Supports Xtensa Cores

Need to create a virtual mixed-architecture SOC? Try using Virtutech's Simics, which allows engineers to adopt a virtualized systems development approach, resulting in faster product definition, development and deployment in comparison to traditional hardware centric approaches. It supports over 40 cores! See the press release at http://www.tensilica.com/news/294/330/Virtutech-Simics-Processor-Support-Grows-to-Include-Multicore-RMI-XLR-MIPS64-and-Configurable-Tensilica-Xtensa-Cores.htm