Validity Sensors Licenses Two Tensilica Processors for High-Volume Fingerprint Sensors

"Power, performance and die size are critical factors in our leading edge sensor designs," stated Alex Erhart, EVP of products at Validity Sensors. "Moving up from a 16-bit controller to a 32-bit controller creates a lot of opportunities to add enhanced features that need to be balanced with the area and power impact of a higher end controller. Tensilica's processors give us the speed we need with the lowest power and minimal die size. We were particularly impressed with the ability to customize the processors for our exact application requirements."

For more, see http://www.tensilica.com/news/293/330/Validity-Sensors-Licenses-Two-Tensilica-Processors-for-High-Volume-Fingerprint-Sensors.htm

New SW Design Center Supports Audio/Video and Security Apps

Calsoft is Tensilica's newest software design center. "We joined Tensilica's partner program because we have seen increasing interest in Tensilica's customizable processors among designers of next-generation video and audio chips," Sanjay Dube, Calsoft's director of business development. "As we combine our expertise in embedded technologies with skills in audio-video codec development and security applications, we are able to offer a unique set of services, including developing audio-video codecs, porting VoIP stacks, board support packages, software integration, protocols testing and QA. Now, equipped with Tensilica's full tool set, we can help companies with a variety of complex and diverse software requirements."

http://tinyurl.com/create.php

Blue Wonder Communications Uses Tensilica for LTE

"New design approaches are needed to successfully implement the LTE and LTE Advanced standards," stated Dr. Peter Meyer, managing director and head of development at Blue Wonder Communications. "The traditional approach of using hardwired logic for the performance-intensive PHY layer datapath simply won't work. Because LTE systems run at such high data rates, it would require millions of gates of logic developed with RTL (register transfer level) methods - and that creates a huge verification hurdle. Using Tensilica's automated processor creation tools we are able to quickly generate customized DPUs delivering the performance levels of custom hardware with the programmability of a processor."

See the press release at http://www.tensilica.com/news/291/330/Blue-Wonder-Communications-to-Develop-LTE-Baseband-IP-Using-Multiple-Optimized-Tensilica-Dataplane-Processors.htm

A Processor and DSP IP Checklist

"A Processor and DSP IP Selection Checklist" - This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle. http://www.tensilica.com/products/literature-docs/white-papers/ia-processor-dsp-ia-processor-and-dsp-iip-selection-checklist.htm

New white paper: 10 Tips for Successful SOC Design

One way to ensure SOC design success is to start out in the right direction. That's the purpose of this White Paper-to help you start out in the right direction. These ten SOC design tips come straight from the hard-won experience we have gotten from working with our customers on many types of SOC design projects for wireless, multimedia, communications, networking, computing, and storage applications.

http://www.tensilica.com/products/literature-docs/white-papers/10-tips-for-soc-design/

See How Easy it is to Configure a Processor

Yes, you can do this! Watch the video. Chris Rowen, our CTO, shows just how easy it is to pick the configuration options you need for your processor core: http://www.tensilica.com/products/xtensa-customizable/configurable.htm

See how Epson Uses Multiple Xtensa Processors in Printers

What's the secret behind Epson's Realoid chip inside their inkjet printers? It's not a secret any more. Find out how multiple Xtensa processor cores give more flexibility and programmability over previous generation hardwired RTL solution
http://www.tensilica.com/products/literature-docs/success-stories/epson-printers.htm

The ConnX 545Ck - the fastest DSP core ever

See why BDTI benchmarked the ConnX 545Ck as the fastest DSP core they've ever tested. See http://www.tensilica.com/products/dsps/545ck-new.htm

Accelerated Interrupt Handling Ap Note

Fast interrupt handling is important to system throughput and responsiveness. This application note describes a method to use existing Xtensa features and configuration options to support very fast interrupt handling. This note focuses on the interrupt handling case, i.e, that case where one task is running, but is preempted at some random point by an external or timer interrupt, which then performs an independent task.
http://tinyurl.com/ku4uwz

New White Paper on DSP

New white paper: Optimizing a DSP Architecture for Wireless Baseband. See http://tinyurl.com/ll25y8