DesignArt Networks Picks Xtensa LX2 for WiMax

“By using Tensilica’s Xtensa LX2 configurable processors in our SOC, we took our platform to a higher level of flexibility, and we are able to bring a highly configurable silicon platform to our customers. The benefits are clear – better ability of tracking customer requirements and standards evolution, as well as an in-field software upgradeable network infrastructure,” stated Oz Barak, CEO, DesignArt Networks.

“In the PHY, the powerful Xtensa LX2 DSP core enables the implementation of various MIMO receiver configurations. In the MAC layer, the Xtensa LX2 processors are the engine of the embedded high packet rate network processor, forming a highly-configurable design to track the future 802.16e standard evolution, as well as the emerging 802.16j standard. The robustness and sophistication of the Xtensa toolset allowed us to have packets traversing an RTL simulation on day 2 of the development effort. Today, these multi-core subsystems are up and running on the FPGA boards in our integration labs, with several months of testing already completed.”

For more information, see http://www.tensilica.com/news_events/pr_2007_06_14.htm

Why High MHz Does Not Mean High Performance

Do you think that high MHz = high performance? The PC industry tried to teach us that, but it simply isn't true. There are a lot of other factors, and often you can get higher performance out of an optimized lower MHz processor. See the article on SOCcentral.com at:
http://www.soccentral.com/results.asp?CatID=488&EntryID=22911

Achieving Very High Performance in the Networking Data Plane

Sign up now for Tensilica's next Techonline Seminar: Achieving Very High Performance in the Networking Data Plane. We'll be giving this seminar on Wednesdy, June 27 at 10 am Pacific time (1 pm EST). Sign up at
http://seminar2.techonline.com/registration/distrib.cgi?s=1096&d=1062

Tensilica Announces Industry’s First MP3 Decoder Under 6 MHz

Tensilica has optimized the MP3 decoder for its Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. This MP3 decoder now runs at the lowest power and is the most efficient in the industry, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65nm LP process (including memories). This makes Tensilica’s Xtensa HiFi 2 Audio Engine ideal for adding MP3 playback to cellular phones, where current carrier requirements are for 100 hours of playback time on a battery charge, and increasing to 200 hours in the near future.

This 5.7 MHz requirement includes the entire MP3 decode functionality, including MPEG container parsing and variable length decoding (VLD, also known as Huffman decoding). Some competing offerings are merely accelerator blocks that exclude portions of the complex control code in MP3 such as VLD, and thus rely on a processor to perform VLD decoding. Tensilica’s 5.7 MHz figure is all inclusive.

For more information, see http://www.tensilica.com/news_events/pr_2007_05_16.htm

Two Korean Universities License Xtensa

The CoSoC (Center of System on Chip design technology) of Seoul National University is using Xtensa processors in the classroom and has announced their third annual SOC design contest, which will, for the first timie, accept designs that use Xtensa processors.

The KAIST (Korea Advanced Institute of Science and Technology) has licensed Xtensa to develop multimedia SOC designs.

Our agreement with these two universities underscores our dedication to working with universities around the world to train next-generation design engineers. We now have over 80 universities worldwide that use Xtensa processors in their research and/or classrooms.

Great new article on our video processor

Find out what's inside the Diamond Video Engine for encoding/decoding H.264/AVC video. Video/Imaging DesignLine.com posted Steve Leibson's article "Anatomy of a hardware video codec" today at http://www.videsignline.com/howto/videoprocessing/199500920.

SRS Labs Ports TruSurround HD for HDTV

SRS Labs has ported its TruSurround HD virtual sound audio technology to Tensilica’s HiFi 2 Audio Engine for Xtensa processors and the Diamond Standard 330HiFi Audio Processor. SRS TruSurround HD is ideal for designers of system-on-chip (SOC) devices for the midrange and high-end digital television and digital home entertainment markets. Tensilica’s HiFi 2 Audio Engine is the most popular commercial audio processor core for SOC designs, and this year Tensilica’s customers are forecasting they will ship 100 million HiFi Audio Engine enabled processor cores in a wide variety of consumer devices.
For more information, see http://www.tensilica.com/news_events/pr_2007_05_08.htm

Commetrex Fax Solutions Now Available

Commetrex’ fax technologies now support Tensilica’s Xtensa configurable and Diamond Standard processor cores. This proven solution, already shipping in high volume, will give Tensilica’s customers a complete, off-the-shelf solution for products requiring built-in fax capabilities. For more information, see http://www.tensilica.com/news_events/pr_2007_05_02.htm

Tensilica Adds Support for Low-Cost, Hardware-Based Simulations of Diamond Standard Processors

Tensilica is now supporting Avnet LX60 FPGA boards for high-speed hardware-based simulations of its Diamond Standard processor family. Software developers can use these popular, very-low-cost FPGA boards, which allow Diamond Standard processor cores to run on Xilinx Virtex-4 FPGAs, to speed their software design, debug and program optimization processes. For more information, see http://www.tensilica.com/news_events/pr_2007_04_17.htm

CMC Microsystems Provides Hundreds of Canadian University Researchers with Access to Tensilica Prototyping Technology for Designs Using Xtensa LX2

CMC Microsystems has upgraded its license for Tensilica’s Xtensa LX2 processor generator, boosting the prototyping capability available to university researchers through Canada’s System-on-Chip Research Network (SOCRN).

This technology, which helps optimize designs by reducing the power and increasing the efficiency of the chip, will enable engineers at 36 participating SOCRN universities to create FPGA-based hardware prototypes for designs that include customized versions of the Xtensa LX2 processor. The agreement will enable wider use and application of system-on-chip (SOC) designs with Tensilica’s Xtensa-based configurable processor technology.

For more information, see http://www.tensilica.com/news_events/pr_2007_04_03.htm