90nm announcements today

Today Tensilica issued three press releases that show that our Xtensa processors are proven in 90nm technology. See the front page of our new web site, www.tensilica.com, to read the text of these announcements. You'll find that our Xtensa LX processor reached the highest clock rate of any licensable 32-bit processor on the market in 90 nm technology. We have statistics from STMicroelectronic's runs and TSMC simulations. We also have details on the EDA flow used, with tools from Cadence and Synopsys.

Why is this so important? It means that our base architecture, without any modifications, is superior to other 32-bit architectures. The Xtensa processor is ideal for applications ranging from a simple control processor to applications where performance is critical.

New Web Site

Yes, we've been kind of qiet with our blog this summer. But we didn't take the summer off. We're getting ready to launch our new web site. We're adding two important new sections: Methodology and Markets. Lots of new, good content. A more sophisticated look and feel. And it's been a lot of work. We're in final testing now, and we plan to go "live" this weekend. Check it out at www.tensilica.com.

See Tensilica at DAC

You won't be able to miss Tensilica if you're going to DAC next week in Anaheim, CA. We caught baseball fever from playing the Konami baseball game (Xtensa processor diving the video inside) and you can try, too! Enter our raffle for 2 world series tickets! Other features include:

Tuesday, June 14 11:30 AM- 12:15 PM, Booth 2269 PAVILION PANELESL: Is it Just MATLAB® and Excel Spreadsheets? Grant Martin - moderator

Wednesday, June 15 2:00-5:00 PM Hands-on Tutorial: Using Configurable Processors to Replace RTL Blocks Register Now!

Thursday, June 16 Session 43, Room 210AB 10:30 AM - 12:00 PM Implementing Low-Power Configurable Processors - Practical Options and TradeoffsAshish Dixit - presenter

Thursday, June 16Session 47, Room 210CD 12:15 - 1:45 PM Smart Diagnostics for Configurable Processor Verification Sadik Ezer, presenter

Thursday, June 16 Session 52, Room 210CD 4:30 - 6:00 PM - Panel: Platform ASIC Apprentices: Who Will Survive Your Boardroom? Steve Leibson, presenter

Friday, June 17 Friday Tutorial, Room 207ABC 9:00 AM - 5:00 PM #6 - Design of SoC with Embedded Processors Chris Rowen - CEO, speaker

Antonio J. Viana - New Sr. VP of Sales

Antonio J. Viana has joined Tensilica as senior vice president of worldwide sales. Viana joined Tensilica from ARM, Ltd., where he was vice president of North American sales.

“Tensilica has intelligently automated the customization of processors to achieve RTL-equivalent performance and much lower power dissipation,” stated Viana. “Considering all of the challenges of SOC design, time-to-market is typically one of the most significant. Tensilica’s technology is best poised to help customers meet the current and future challenges of SOC design, in particular, time-to-market. I am very excited to be a part of the Tensilica family.”

Agilent Licenses Xtensa for Image Processing

Agilent Technologies, Inc.’s Imaging Systems Division has signed a broad technology-access agreement to license Tensilica’s Xtensa V and Xtensa LX configurable processor technologies for next-generation products. This follows the successful deployment of Xtensa V processors by Agilent in several recently introduced imaging products.
For more information, see http://www.tensilica.com/html/pr_2005_05_19.html.

ARM's BDTI Benchmark Scores

On May 16 ARM announced “Class-leading” BDTi benchmark scores (see http://www.arm.com/news/9103.html). However, ARM’s “class” only included their processor and the MIPS 24Kc processor.

There were several other processors that ARM decided not to mention, including Tensilica’s Xtensa LX processor, which achieved a 5x higher score than the ARM11 processor. Other processors not mentioned but also surpassing ARM’s results include the CEVA-X1620, LSI Logic’s ZSP500, StarCore SC1200, and StarCore SC1400. For full BDTI results, see http://www.bdti.com/bdtimark/core_scores.pdf.

Xtensa LX Processor Tops EEMBC Networking 2.0 Benchmarks

Tensilica's Xtensa LX processor achieved the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBCÒ). Xtensa LX is the first licensable processor core to complete certification on this challenging benchmark suite.

EEMBC benchmark scores, based on simulation, show that an optimized Xtensa LX processor core is significantly faster on a per-MHz basis than the only two other processors certified to date, the 1GHz PowerPC 750GX and 1.4 GHz PowerPC MPC7447A, both of which are full-chip, standard product processors. The Xtensa LX processor delivers this outstanding performance while simultaneously delivering a 4X code density advantage and more than a 100X advantage in both die area and power dissipation.

For all the details on this important benchmark, see http://www.tensilica.com/html/pr_2005_05_16.html.

Tensilica Preview at Spring Processor Forum

Next Wednesday, May 18, Tensilica will preview our next-generation audio engine at the Spring Processor Forum in San Jose (see http://www.in-stat.com/spf/05/conf.htm ). We'll have this product ready for a formal announcement in the fall, but if you want a sneak preview, stop by and hear what we have to say. By using a configurable processor, we're able to really optimize the design for high-speed audio streams.

Tensilica and EVE Speed SoC Development Times

Tensilica is working with Emulation and Verification Engineering (EVE) to speed the design of complex SoCs with multiple Xtensa processors. Tensilica’s customers will be able to download pre-verified RTL code produced by Tensilica’s Xtensa Processor Generator into EVE’s hardware prototyping platform for integrated whole-chip design verification. Tensilica’s Xtensa Xplorer development environment will be linked to EVE’s ZeBu hardware-based verification product to provide hardware/software co-verification and improve overall SoC simulation and debugging. By providing our users with easy access to EVE’s ZeBu prototyping platform, they should be able to quickly verify their entire SOC designs.

Great Article by Jack Ganssle

Jack Ganssle, the guru for many software developers, wrote a great piece for Embedded Systems Programming and you can see it at http://www.embedded.com/showArticle.jhtml?articleID=161600589. He shows that the best way to cut software costs is to divide and conquer. By dividing projects into smaller, more manageable tasks that each run on its own processor, overall software costs can be cut significantly. Tensilica's customers have been doing this for years. By employing multiple configurable processors, each tailored to the exact task at hand, these customers are cutting design time and software development time.