Tensilica Participates in Synopsys TLMCentral Web Portal for Transaction-Level Model Access

TLMCentral aggregates information about free and commercial system-level models of common system-on-chip (SoC) components from leading semiconductor IP vendors, tool providers, service companies and universities. TLMCentral is an open portal that will ease and accelerate the development of virtual prototypes across the industry. It is available at no cost to users and providers of transaction-level models.

Transaction-level models raise designer productivity by increasing the level of abstraction at which they design. TLMs are predominantly used in virtual prototypes which allow engineers to accelerate their software design schedules by up to nine months and significantly improve the productivity of their software development, hardware/software integration, and system validation tasks. Transaction-level modeling has also contributed to significant productivity gains in architecture design and SoC verification, and the models aggregated on TLMCentral can be applied to those use cases as well. See Synopsys news.

Software Defined Everything - Tensilica's Grant Martin's latest blog

Tensilica's Chief Scientist Grant Martin discusses the challenges of getting the right mix of hardware and software for hardware defined radios. Read his blog post.

Fraunhofer ISS is Tensilica's Newest Authorized Design Center Partners

Wow. If you need someone with tons of experience in audio and multimedia technologies, look at Fraunhofer.

“We look forward to working closely with Tensilica and the wide customer base using Tensilica’s HiFi Audio DSPs, especially for home entertainment, automotive and mobile multimedia,” stated Marc Gayer, head of Embedded Audio at Fraunhofer IIS. “Tensilica’s HiFi Audio DSP architecture is extremely efficient with industry best area and power requirements.” See press release.

Tensilica Now Hiring in Israel

We're looking for a great Field Applications Engineer. Learn more about this posting here.

Visit Tensilica's Linux Wiki Pages

Yes, several Tensilica customers run Linux on their Tensilica IP cores. And we collect information on how best to do that at our Wiki. We've seen Linux running on cores with up to a gigabyte of memory. And while most of our processors run without operating systems in the dataplane, why not match up those dataplane cores with a Tensilica main control processor running Linux as well. Then all the cores will be using the same software tool chain.

Tensilica Customer TranSwitch Announces LTE™ Fixed Wireless Residential Gateway Solution

Last week TranSwitch announced the availability of a new LTE (*Long Term Evolution; a 4G wireless broadband technology) fixed wireless reference design that enables wireless providers to deliver broadband voice, video and data services to homes and enterprises. TranSwitch’s reference design incorporates its Atlanta 2000™ processor and complete software solution which is designed for high performance, real time services under real world network conditions.  The Atlanta 2000 includes Integrated dual RISC cores: 400 MHz Tensilica Xtensa LX with MMU.

Three More Jobs Posted at Tensilica

Check out our full list (we're up to 17 jobs posted now) and see if you know someone that can help Tensilica grow. We're looking for people in Beijing, Pune and Santa Clara.

SRS Labs Expands Portfolio of Advanced Audio Solutions Available for Tensilica HiFi DSP Cores

"Tensilica's HiFi 2 and HiFi EP DSP cores are the popular choice of our platform partners," said Joanna Skrdlant, Senior Director, Global Platform Partner Program. "Over the course of a year, we've seen a substantial increase in our licensee's projects based upon chips designed with Tensilica HiFi 2 and HiFi EP DSP core solutions. Given this accelerating demand, we made it a top priority to port our latest audio technologies to the HiFi cores."

See the full press release and details here.

Cavium Picks Tensilica for Next-Generation Wireless Broadband Application

 The Tensilica products selected include Tensilica's popular baseband IP specialized for channel decode applications and signal processing to achieve best-in-class speed, power and performance. Cavium is a leading provider of semiconductor products that enable intelligent processing for networking, wireless, storage and video.

"Tensilica's IP will help us achieve best-in-class speed/power/performance, faster time-to-market and great flexibility through efficient programmability," stated Raj Singh, general manager, Wireless Broadband Group, Cavium. "We were particularly delighted with Tensilica's understanding of the computational processing required for wireless broadband and their great technical support."

See press release.

This Week - Tensilica Seminars in Taiwan and Japan

It's last chance time to sign up for Tensilica's seminars in Taiwan on Sept. 14 and in Japan on Sept. 16. Visit this seminar to find out about Tensilica’s wide range of DSP IP cores. Tensilica actually has more varieties of DSP IP cores than any other vendors, plus we offer you the ability to easily customize our base processor for the DSP functions you need for your application.

Our base processor is also an excellent controller, allowing you to do the control functions along with the DSP functions or even use it as a software tools compatible controller for your chip design.

From a basic 2-MAC DSP all the way up to the fastest DSP in the industry, our 128-MAC baseband processor for LTE Advanced, Tensilica can help you get the DSP performance you need in a highly efficient IP core. As examples of the performance you can get from our technology, we’ll showcase our audio and baseband DSPs in this free seminar.

Audyssey’s Sound Correction Technologies Come To Tensilica’s HiFi Audio DSP

Audyssey's audio technology fixes acoustical and perceptual problems to reproduce content as close to the original as possible. This helps ensure that consumers get the best sound from their home theaters, DTVs, automobiles and mobile devices. Audyssey's technology provides expanded surround sound options, preserves immersion at low volumes, helps eliminate distortion, maintains optimal volume when people watch TV, and can even prevent low frequencies from disturbing the neighbors. Read press release.

EtherWaves Expands Digital Radio Choice – Adds Support for Tensilica Dataplane Processor Cores

The new ClearSignal RF agnostic design broadens SoC designers' choice to immediately add Digital Radio capability to mobile devices, while keeping the required low power consumption. This ClearSignal implementation takes advantage of Tensilica's ConnX Vectra LX DSP Engine and other architecture optimizations for achieving a typical DAB channel reception at clock rates as low as 50 MIPS. Read the press release for more details.

Tensilica's Xtensa 9 or Xtensa LX4? What's the difference in Customizable Processors?

Xtensa LX4 is built on top of the Xtensa 9 architecture, so it's important to evaluate both to see what processor is best for your application. This page has an interesting comparison between the two.

White Paper: 10 Tips for Successful SOC Design

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.