Whitepaper: Using Processors in the SOC Dataplane

Now for your after Thanksgiving reading pleasure - find out how you can use processors in the SOC dataplane (they're not just for control any more) - by connecting processors directly to RTL - avoiding the bus and getting high-speed data throughput.

Happy Thanksgiving Week everyone

It's a good time to be thankful for all of the interesting people who work in technology - they make my life very interesting and are responsible for such great innovative products. Happy Thanksgiving everyone. We'll be closed in the US on Thursday and Friday.

Samsung Signs for HIFi 2 for Home Entertainment Products

The Digital Media & Communications Business of Samsung Electronics has signed a multi-year license to Tensilica's HiFi 2 Audio DSPfor use in Samsung's multimedia system products after a successful previous deployment in Samsung's System LSI Division. Tensilica's HiFi architecture is the most popular commercial audio core for system-on-chip designs.

"We selected the Tensilica HiFi Audio DSP because of its impressive performance capabilities and because of the breadth of software codecs available," stated K.W. Chun, vice president, Digital Media & Communications Business of Samsung Electronics. "The HiFi 2 Audio DSP can execute the most demanding multi-channel audio algorithms at remarkably low MHz and low power."

How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors

HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.

White paper on Blu-ray Audio

Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.

"Trends in Heterogeneous Multicore SoCs" by Grant Martin

Restructuring the problems once reserved for General-Purpose Processors (GPPs) into application-specific units creates interesting options for designers. Grant discusses the architecture for Application-Specific Instruction set Processors (ASIPs) matched to dataplane tasks and more. See http://www.embedded-computing.com/articles/id/?4304

New IEEE Computer Article features Work at Lawrence Berkely Labs

See the article in the Nov. issue of Computer titled "Energy-Efficient Computing for Extreme-Scale Science" by CTO Chris Rowen and others about the work on low-power design at Lawrence Berkeley Labs. http://www.tensilica.com/uploads/pdf/ieee_computer_nov09.pdf

Everything You Know about Microprocessors is Wrong

Here's a great web seminar that's archived, so you can view it any time. Many system-engineering concepts and "best practices" with respect to system design are no longer valid at the chip level. For example, bus-centric design--made popular by the introduction of the first commercial microprocessor in 1971--continues to dominate on-chip design 36 years later even though nanometer silicon has completely changed the rules of system interconnect.

Xtensa 8 and LX3 are out - it's time to party

Today we have a company-wide bowling tournament offsite to celebrate the release of our eight generation processors - Xtensa 8 and Xtensa LX3. Fun for all!

What's the fastest route from C algorithm to gates?

You've got an algorithm written in C. You can quickly see how that will run on a standard processor core, but you'd be amazed how much faster that algorithm can run on a specially tailored processor. A simple example is an audio stream. If the datapath of a processor is specially tailored just for audio data, that's going to go through the processor much faster, and therefore better quality sound. The same holds true for other data-intensive applications, especially when the datapath doesn't exactly fit into 32 bit words. Find out more from this white paper: http://www.tensilica.com/products/literature-docs/white-papers/fast-path-from-c-to-gates/

Xtensa 8 or Xtensa LX3?

Xtensa LX3 is a superset of Xtensa 8 and adds some very powerful features. Find out more at http://www.tensilica.com/products/xtensa-customizable/xtensa_choice.htm

Grant Martin at Synopsys Interoperabity Forum Tomorrow 1:15 in Santa Clara

See our Chief Scientist talk in the System-level design section - topic: Getting high with a little help from my friends: Configurable processor interoperability with ESL tools.

Xtensa LX3 - 10 GigaMAC/Sec DSP Performance, tops 1 GHz

The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.037 mm² and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm² (post place-and-route 45GS) and consuming just 170 mW (including leakage).

Grant Martin in Tutorial at ICCAD 4:30 today

Embedded Processors, Methods and Applications: Computer Architects Perspective

As feature sizes diminish and transistors multiply, designers are compelled to move to higher levels of abstraction to overcome the productivity gap. Increasingly designers use processors as the main module in embedded system design. The available choices to the modern designer include processor (which are both non-configurable and configurable), DSP and GPU cores. This tutorial explores the available processors, details methodologies and explains applications.

The tutorial is divided into three parts: the first will explore the field of embedded processors; the second will look design methodologies based on embedded processors; the third, will describe an application in detail. This tutorial will be presented by three experienced researchers with industrial and academic experience, and will benefit students, researchers, and design engineers.

Speakers:

Grant Martin - Tensilica, Inc.
Sri Parameswaran - Univ. of New South Wales
Anand Raghunathan - Purdue Univ.
http://www.iccad.com/events/eventdetails.aspx?id=106-3-E