Sign up for our Web Seminar: The 5 Pitfalls of 4G Baseband Design

Sign up now for our web seminar next Tuesday, October 27, at 11 am pacific daily time. It will be recorded, so you can watch it later, too. Chris Rowen, our CTO, will talk about the emerging LTE standard, which is complex, requires extraordinary computation throughput and much better power efficiency than previous wireless baseband PHY subsystems. Because of the complexity, designers are taking many different approaches to chip design for LTE.

This webinar explores five significant challenges faced by designers of efficient digital basebands, including pitfalls in LTE's many modes, excessive cost and power, the "million MIPS" hurdle of Turbo decoding, and the dilemma of choosing the right communications among the LTE building blocks. This webinar uses detailed examples from an end-to-end LTE PHY baseband architecture to highlight the key dos and don'ts. http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=tensilica_oct2709

More Configuration Optons Than Ever in Xtensa 8

Want your processor core your way but don't want to work hard at it? Just look at all of the configuration options you get with Xtensa 8. Just click on a button or use a pull-down menu to make your selections - then you can get your processor you way. See http://www.tensilica.com/products/xtensa-customizable/xtensa/configurability.htm

Xtensa 8 - Our 8th Generation Processor with Novel I/O

By embedding functionality right into the processor datapath itself, designers can use the Xtensa 8 DPU to not only perform control functions, but also some of the finite state machine tasks that manage RTL blocks and some of the RTL functionality as well. This makes for a smaller, more efficient chip design, and it significantly reduces the verification challenges associated with new RTL designs. See http://www.tensilica.com/products/xtensa-customizable/xtensa.htm

Monday's Big News - Stay Tuned!

Busy today putting the finishing touches on the website update for a new processor announcement on Monday. Very cool stuff.

Why use Tata's Ro-SES OS?

Today we announced that Tata Elxsi's RoS-ES (Real Time Operating System for Embedded Systems) OS is now available for Xtensa and Diamond Standard processors. So why use a small OS like this rather than Linux? When you're using deeply embedded controllers in the dataplane, you don't need all the overhead of most OSes. Tata Elxsi's RoS-ES is a compact real-time operating system (RTOS) that provides an impressive array of capabilities making it well suited to networking and consumer electronics applications. More information on the RoS-ES RTOS is available at www.tataelxsi.com/roses.

Multiple Codec Operation Apnote

This application note describes a multi-stream audio decoder test bench that works without needing a threading operating system. A software test bench is provided for the Diamond 330HiFi processor that supports decoding and audio mixing of an arbitrary number of homogenous or heterogeneous audio streams. This application note describes the test bench, and discusses the coding techniques used to reduce memory requirements and to synchronize/mix audio decoded from multiple streams.
http://www.tensilica.com/products/literature-docs/application-notes/audio-application-notes/multiple-audio-codec.htm

Hi Fi Audio DSP Gets DTS-HD Master Audio Certification

Tensilica's HiFi Audio DSP is the first IP core to achieve certification. Having the HiFi DSP IP core certified independent of the choice of silicon implementation will significantly ease Tensilica's customers' efforts to design Blu-ray Disc and Audio Video Receiver SOCs and complete chip and system level certification with DTS.

White Paper: Get Your ASICs Off the Bus

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.
http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/

Interesting apnote on Optimizing for Low Power

It's amazing how little decisions can make a big difference in energy consumption. Read our apnote: Optimizing for Energy using the Xenergy Energy Optimizator Tool.
http://www.tensilica.com/products/literature-docs/application-notes/xtensa-tools/xenergy-energy-optimizator.htm

Whitepaper: How to Manage Video Frame-Processing Time Deviations

Whitepaper: How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors - you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after. http://www.tensilica.com/products/literature-docs/white-papers/video-frame-processing/

CTO Chris Rowen Giving Baseband Talk Tomorrow at SOC Conf in Tampere

From 13.20-14.40 Rowen will discuss A DSP architecture optimized for wireless baseband. The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations. http://soc.cs.tut.fi/2009/Technical_program.php

White Paper: TIE - The Fast Path to High Performance Embedded SOC Processing

TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power. http://www.tensilica.com/products/literature-docs/white-papers/tie---the-fast-path.htm

Excellent AMD ATI Video with Xtensa

Tensilica's processors configured to accelerate video stream decoding are an ingredient in every UVD-powered AMD ATI graphics chip, including those iwth ATI Avivo HD video and dipslay techology, which provdes PC users with crisp images, smooth videos and true-to-life colors. UVD is a dedicated video decode processing unit introduced with the ATI Radeon HD 2000 series graphics processors that offloads the CPU from the decoding process. UVD technology reduces power use, helps decrease system noise and helps to increase notebook battery life during HD video playback. AMD's graphics products provide for DirectX10 gaming and allow PCs to be hooked up to big-screen TVs with HDMI and built-in 5.1 surround sound audio to enjoy Blu-ray and HD DVD movies. http://www.tensilica.com/markets/customer-gallery/graphics.htm